cpu/arm920t/start.S

   1 /*
   2  *  armboot - Startup Code for ARM920 CPU-core
   3  *
   4  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   5  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
   6  *  Copyright (c) 2002  Gary Jennejohn <gj@denx.de>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27
  28 #include <config.h>
  29 #include <version.h>
  30
  31
  32 /*
  33  *************************************************************************
  34  *
  35  * Jump vector table as in table 3.1 in [1]
  36  *
  37  *************************************************************************
  38  */
  39
  40
  41 .globl _start
  42 _start: b       reset
  43         ldr     pc, _undefined_instruction
  44         ldr     pc, _software_interrupt
  45         ldr     pc, _prefetch_abort
  46         ldr     pc, _data_abort
  47         ldr     pc, _not_used
  48         ldr     pc, _irq
  49         ldr     pc, _fiq
  50
  51 _undefined_instruction: .word undefined_instruction
  52 _software_interrupt:    .word software_interrupt
  53 _prefetch_abort:        .word prefetch_abort
  54 _data_abort:            .word data_abort
  55 _not_used:              .word not_used
  56 _irq:                   .word irq
  57 _fiq:                   .word fiq
  58
  59         .balignl 16,0xdeadbeef
  60
  61
  62 /*
  63  *************************************************************************
  64  *
  65  * Startup Code (reset vector)
  66  *
  67  * do important init only if we don't start from memory!
  68  * relocate armboot to ram
  69  * setup stack
  70  * jump to second stage
  71  *
  72  *************************************************************************
  73  */
  74
  75 _TEXT_BASE:
  76         .word   TEXT_BASE
  77
  78 .globl _armboot_start
  79 _armboot_start:
  80         .word _start
  81
  82 /*
  83  * These are defined in the board-specific linker script.
  84  */
  85 .globl _bss_start
  86 _bss_start:
  87         .word __bss_start
  88
  89 .globl _bss_end
  90 _bss_end:
  91         .word _end
  92
  93 #ifdef CONFIG_USE_IRQ
  94 /* IRQ stack memory (calculated at run-time) */
  95 .globl IRQ_STACK_START
  96 IRQ_STACK_START:
  97         .word   0x0badc0de
  98
  99 /* IRQ stack memory (calculated at run-time) */
 100 .globl FIQ_STACK_START
 101 FIQ_STACK_START:
 102         .word 0x0badc0de
 103 #endif
 104
 105
 106 /*
 107  * the actual reset code
 108  */
 109
 110 reset:
 111         /*
 112          * set the cpu to SVC32 mode
 113          */
 114         mrs     r0,cpsr
 115         bic     r0,r0,#0x1f
 116         orr     r0,r0,#0xd3
 117         msr     cpsr,r0
 118
 119 /* turn off the watchdog */
 120 #if defined(CONFIG_S3C2400)
 121 # define pWTCON         0x15300000
 122 # define INTMSK         0x14400008      /* Interupt-Controller base addresses */
 123 # define CLKDIVN        0x14800014      /* clock divisor register */
 124 #elif defined(CONFIG_S3C2410)
 125 # define pWTCON         0x53000000
 126 # define INTMSK         0x4A000008      /* Interupt-Controller base addresses */
 127 # define INTSUBMSK      0x4A00001C
 128 # define CLKDIVN        0x4C000014      /* clock divisor register */
 129 #endif
 130
 131 #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
 132         ldr     r0, =pWTCON
 133         mov     r1, #0x0
 134         str     r1, [r0]
 135
 136         /*
 137          * mask all IRQs by setting all bits in the INTMR - default
 138          */
 139         mov     r1, #0xffffffff
 140         ldr     r0, =INTMSK
 141         str     r1, [r0]
 142 # if defined(CONFIG_S3C2410)
 143         ldr     r1, =0x3ff
 144         ldr     r0, =INTSUBMSK
 145         str     r1, [r0]
 146 # endif
 147
 148         /* FCLK:HCLK:PCLK = 1:2:4 */
 149         /* default FCLK is 120 MHz ! */
 150         ldr     r0, =CLKDIVN
 151         mov     r1, #3
 152         str     r1, [r0]
 153 #endif  /* CONFIG_S3C2400 || CONFIG_S3C2410 */
 154
 155         /*
 156          * we do sys-critical inits only at reboot,
 157          * not when booting from ram!
 158          */
 159 #ifdef CONFIG_INIT_CRITICAL
 160         bl      cpu_init_crit
 161 #endif
 162
 163 relocate:                               /* relocate U-Boot to RAM           */
 164         adr     r0, _start              /* r0 <- current position of code   */
 165         ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 166         cmp     r0, r1                  /* don't reloc during debug         */
 167         beq     stack_setup
 168
 169         ldr     r2, _armboot_start
 170         ldr     r3, _bss_start
 171         sub     r2, r3, r2              /* r2 <- size of armboot            */
 172         add     r2, r0, r2              /* r2 <- source end address         */
 173
 174 copy_loop:
 175         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 176         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 177         cmp     r0, r2                  /* until source end addreee [r2]    */
 178         ble     copy_loop
 179
 180         /* Set up the stack                                                 */
 181 stack_setup:
 182         ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
 183         sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
 184         sub     r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
 185 #ifdef CONFIG_USE_IRQ
 186         sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 187 #endif
 188         sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 189
 190 clear_bss:
 191         ldr     r0, _bss_start          /* find start of bss segment        */
 192         ldr     r1, _bss_end            /* stop here                        */
 193         mov     r2, #0x00000000         /* clear                            */
 194
 195 clbss_l:str     r2, [r0]                /* clear loop...                    */
 196         add     r0, r0, #4
 197         cmp     r0, r1
 198         ble     clbss_l
 199
 200 #if 0
 201         /* try doing this stuff after the relocation */
 202         ldr     r0, =pWTCON
 203         mov     r1, #0x0
 204         str     r1, [r0]
 205
 206         /*
 207          * mask all IRQs by setting all bits in the INTMR - default
 208          */
 209         mov     r1, #0xffffffff
 210         ldr     r0, =INTMR
 211         str     r1, [r0]
 212
 213         /* FCLK:HCLK:PCLK = 1:2:4 */
 214         /* default FCLK is 120 MHz ! */
 215         ldr     r0, =CLKDIVN
 216         mov     r1, #3
 217         str     r1, [r0]
 218         /* END stuff after relocation */
 219 #endif
 220
 221         ldr     pc, _start_armboot
 222
 223 _start_armboot: .word start_armboot
 224
 225
 226 /*
 227  *************************************************************************
 228  *
 229  * CPU_init_critical registers
 230  *
 231  * setup important registers
 232  * setup memory timing
 233  *
 234  *************************************************************************
 235  */
 236
 237
 238 cpu_init_crit:
 239         /*
 240          * flush v4 I/D caches
 241          */
 242         mov     r0, #0
 243         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 244         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 245
 246         /*
 247          * disable MMU stuff and caches
 248          */
 249         mrc     p15, 0, r0, c1, c0, 0
 250         bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
 251         bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
 252         orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 253         orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
 254         mcr     p15, 0, r0, c1, c0, 0
 255
 256
 257         /*
 258          * before relocating, we have to setup RAM timing
 259          * because memory timing is board-dependend, you will
 260          * find a memsetup.S in your board directory.
 261          */
 262         mov     ip, lr
 263         bl      memsetup
 264         mov     lr, ip
 265
 266         mov     pc, lr
 267
 268
 269 /*
 270  *************************************************************************
 271  *
 272  * Interrupt handling
 273  *
 274  *************************************************************************
 275  */
 276
 277 @
 278 @ IRQ stack frame.
 279 @
 280 #define S_FRAME_SIZE    72
 281
 282 #define S_OLD_R0        68
 283 #define S_PSR           64
 284 #define S_PC            60
 285 #define S_LR            56
 286 #define S_SP            52
 287
 288 #define S_IP            48
 289 #define S_FP            44
 290 #define S_R10           40
 291 #define S_R9            36
 292 #define S_R8            32
 293 #define S_R7            28
 294 #define S_R6            24
 295 #define S_R5            20
 296 #define S_R4            16
 297 #define S_R3            12
 298 #define S_R2            8
 299 #define S_R1            4
 300 #define S_R0            0
 301
 302 #define MODE_SVC 0x13
 303 #define I_BIT    0x80
 304
 305 /*
 306  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 307  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 308  */
 309
 310         .macro  bad_save_user_regs
 311         sub     sp, sp, #S_FRAME_SIZE
 312         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 313         ldr     r2, _armboot_start
 314         sub     r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
 315         sub     r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 316         ldmia   r2, {r2 - r3}                   @ get pc, cpsr
 317         add     r0, sp, #S_FRAME_SIZE           @ restore sp_SVC
 318
 319         add     r5, sp, #S_SP
 320         mov     r1, lr
 321         stmia   r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
 322         mov     r0, sp
 323         .endm
 324
 325         .macro  irq_save_user_regs
 326         sub     sp, sp, #S_FRAME_SIZE
 327         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 328         add     r8, sp, #S_PC
 329         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 330         str     lr, [r8, #0]                    @ Save calling PC
 331         mrs     r6, spsr
 332         str     r6, [r8, #4]                    @ Save CPSR
 333         str     r0, [r8, #8]                    @ Save OLD_R0
 334         mov     r0, sp
 335         .endm
 336
 337         .macro  irq_restore_user_regs
 338         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 339         mov     r0, r0
 340         ldr     lr, [sp, #S_PC]                 @ Get PC
 341         add     sp, sp, #S_FRAME_SIZE
 342         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 343         .endm
 344
 345         .macro get_bad_stack
 346         ldr     r13, _armboot_start             @ setup our mode stack
 347         sub     r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
 348         sub     r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 349
 350         str     lr, [r13]                       @ save caller lr / spsr
 351         mrs     lr, spsr
 352         str     lr, [r13, #4]
 353
 354         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 355         @ msr   spsr_c, r13
 356         msr     spsr, r13
 357         mov     lr, pc
 358         movs    pc, lr
 359         .endm
 360
 361         .macro get_irq_stack                    @ setup IRQ stack
 362         ldr     sp, IRQ_STACK_START
 363         .endm
 364
 365         .macro get_fiq_stack                    @ setup FIQ stack
 366         ldr     sp, FIQ_STACK_START
 367         .endm
 368
 369 /*
 370  * exception handlers
 371  */
 372         .align  5
 373 undefined_instruction:
 374         get_bad_stack
 375         bad_save_user_regs
 376         bl      do_undefined_instruction
 377
 378         .align  5
 379 software_interrupt:
 380         get_bad_stack
 381         bad_save_user_regs
 382         bl      do_software_interrupt
 383
 384         .align  5
 385 prefetch_abort:
 386         get_bad_stack
 387         bad_save_user_regs
 388         bl      do_prefetch_abort
 389
 390         .align  5
 391 data_abort:
 392         get_bad_stack
 393         bad_save_user_regs
 394         bl      do_data_abort
 395
 396         .align  5
 397 not_used:
 398         get_bad_stack
 399         bad_save_user_regs
 400         bl      do_not_used
 401
 402 #ifdef CONFIG_USE_IRQ
 403
 404         .align  5
 405 irq:
 406         get_irq_stack
 407         irq_save_user_regs
 408         bl      do_irq
 409         irq_restore_user_regs
 410
 411         .align  5
 412 fiq:
 413         get_fiq_stack
 414         /* someone ought to write a more effiction fiq_save_user_regs */
 415         irq_save_user_regs
 416         bl      do_fiq
 417         irq_restore_user_regs
 418
 419 #else
 420
 421         .align  5
 422 irq:
 423         get_bad_stack
 424         bad_save_user_regs
 425         bl      do_irq
 426
 427         .align  5
 428 fiq:
 429         get_bad_stack
 430         bad_save_user_regs
 431         bl      do_fiq
 432
 433 #endif
 434
 435         .align  5
 436 .globl reset_cpu
 437 reset_cpu:
 438 #ifdef CONFIG_S3C2400
 439         bl      disable_interrupts
 440 # ifdef CONFIG_TRAB
 441         bl      disable_vfd
 442 # endif
 443         ldr     r1, _rWTCON
 444         ldr     r2, _rWTCNT
 445         /* Disable watchdog */
 446         mov     r3, #0x0000
 447         str     r3, [r1]
 448         /* Initialize watchdog timer count register */
 449         mov     r3, #0x0001
 450         str     r3, [r2]
 451         /* Enable watchdog timer; assert reset at timer timeout */
 452         mov     r3, #0x0021
 453         str     r3, [r1]
 454 _loop_forever:
 455         b       _loop_forever
 456 _rWTCON:
 457         .word   0x15300000
 458 _rWTCNT:
 459         .word   0x15300008
 460 #else /* ! CONFIG_S3C2400 */
 461         mov     ip, #0
 462         mcr     p15, 0, ip, c7, c7, 0           @ invalidate cache
 463         mcr     p15, 0, ip, c8, c7, 0           @ flush TLB (v4)
 464         mrc     p15, 0, ip, c1, c0, 0           @ get ctrl register
 465         bic     ip, ip, #0x000f                 @ ............wcam
 466         bic     ip, ip, #0x2100                 @ ..v....s........
 467         mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
 468         mov     pc, r0
 469 #endif /* CONFIG_S3C2400 */