]>
git.ipfire.org Git - people/ms/u-boot.git/blob - cpu/arm_cortexa8/cpu.c
2 * (C) Copyright 2008 Texas Insturments
5 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
9 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <asm/arch/sys_proto.h>
37 #include <asm/system.h>
40 void l2cache_disable(void);
43 static void cache_flush(void);
50 int cleanup_before_linux(void)
55 * this function is called just before we call linux
56 * it prepares the processor for linux
58 * we turn off caches etc ...
62 /* turn off I/D-cache */
66 /* invalidate I-cache */
70 /* turn off L2 cache */
72 /* invalidate L2 cache also */
73 v7_flush_dcache_all(get_device_type());
76 /* mem barrier to sync up things */
77 asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i
));
89 volatile unsigned int j
;
91 /* ES2 onwards we can disable/enable L2 ourselves */
92 if (get_cpu_rev() >= CPU_3XX_ES20
) {
93 __asm__
__volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i
));
94 __asm__
__volatile__("orr %0, %0, #0x2":"=r"(i
));
95 __asm__
__volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i
));
97 /* Save r0, r12 and restore them after usage */
98 __asm__
__volatile__("mov %0, r12":"=r"(j
));
99 __asm__
__volatile__("mov %0, r0":"=r"(i
));
102 * GP Device ROM code API usage here
103 * r12 = AUXCR Write function and r0 value
105 __asm__
__volatile__("mov r12, #0x3");
106 __asm__
__volatile__("mrc p15, 0, r0, c1, c0, 1");
107 __asm__
__volatile__("orr r0, r0, #0x2");
108 /* SMI instruction to call ROM Code API */
109 __asm__
__volatile__(".word 0xE1600070");
110 __asm__
__volatile__("mov r0, %0":"=r"(i
));
111 __asm__
__volatile__("mov r12, %0":"=r"(j
));
116 void l2cache_disable()
119 volatile unsigned int j
;
121 /* ES2 onwards we can disable/enable L2 ourselves */
122 if (get_cpu_rev() >= CPU_3XX_ES20
) {
123 __asm__
__volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i
));
124 __asm__
__volatile__("bic %0, %0, #0x2":"=r"(i
));
125 __asm__
__volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i
));
127 /* Save r0, r12 and restore them after usage */
128 __asm__
__volatile__("mov %0, r12":"=r"(j
));
129 __asm__
__volatile__("mov %0, r0":"=r"(i
));
132 * GP Device ROM code API usage here
133 * r12 = AUXCR Write function and r0 value
135 __asm__
__volatile__("mov r12, #0x3");
136 __asm__
__volatile__("mrc p15, 0, r0, c1, c0, 1");
137 __asm__
__volatile__("bic r0, r0, #0x2");
138 /* SMI instruction to call ROM Code API */
139 __asm__
__volatile__(".word 0xE1600070");
140 __asm__
__volatile__("mov r0, %0":"=r"(i
));
141 __asm__
__volatile__("mov r12, %0":"=r"(j
));
145 static void cache_flush(void)
147 asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));