cpu/arm_cortexa8/omap3/syslib.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Richard Woodruff <r-woodruff2@ti.com>
   6  * Syed Mohammed Khasim <khasim@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/mem.h>
  27 #include <asm/arch/clocks.h>
  28 #include <asm/arch/sys_proto.h>
  29
  30 /************************************************************
  31  * sdelay() - simple spin loop.  Will be constant time as
  32  *  its generally used in bypass conditions only.  This
  33  *  is necessary until timers are accessible.
  34  *
  35  *  not inline to increase chances its in cache when called
  36  *************************************************************/
  37 void sdelay(unsigned long loops)
  38 {
  39         __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
  40                           "bne 1b":"=r" (loops):"0"(loops));
  41 }
  42
  43 /*****************************************************************
  44  * sr32 - clear & set a value in a bit range for a 32 bit address
  45  *****************************************************************/
  46 void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
  47 {
  48         u32 tmp, msk = 0;
  49         msk = 1 << num_bits;
  50         --msk;
  51         tmp = readl((u32)addr) & ~(msk << start_bit);
  52         tmp |= value << start_bit;
  53         writel(tmp, (u32)addr);
  54 }
  55
  56 /*********************************************************************
  57  * wait_on_value() - common routine to allow waiting for changes in
  58  *   volatile regs.
  59  *********************************************************************/
  60 u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
  61                   u32 bound)
  62 {
  63         u32 i = 0, val;
  64         do {
  65                 ++i;
  66                 val = readl((u32)read_addr) & read_bit_mask;
  67                 if (val == match_value)
  68                         return 1;
  69                 if (i == bound)
  70                         return 0;
  71         } while (1);
  72 }