cpu/arm_cortexa8/s5pc1xx/clock.c

   1 /*
   2  * Copyright (C) 2009 Samsung Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  * Heungjun Kim <riverful.kim@samsung.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/clock.h>
  28
  29 #define APLL    0
  30 #define MPLL    1
  31 #define EPLL    2
  32 #define HPLL    3
  33 #define VPLL    4
  34
  35 #define CLK_M   0
  36 #define CLK_D   1
  37 #define CLK_P   2
  38
  39 #ifndef CONFIG_SYS_CLK_FREQ_C100
  40 #define CONFIG_SYS_CLK_FREQ_C100        12000000
  41 #endif
  42 #ifndef CONFIG_SYS_CLK_FREQ_C110
  43 #define CONFIG_SYS_CLK_FREQ_C110        24000000
  44 #endif
  45
  46 unsigned long (*get_pclk)(void);
  47 unsigned long (*get_arm_clk)(void);
  48 unsigned long (*get_pll_clk)(int);
  49
  50 /* s5pc110: return pll clock frequency */
  51 static unsigned long s5pc100_get_pll_clk(int pllreg)
  52 {
  53         struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
  54         unsigned long r, m, p, s, mask, fout;
  55         unsigned int freq;
  56
  57         switch (pllreg) {
  58         case APLL:
  59                 r = readl(&clk->apll_con);
  60                 break;
  61         case MPLL:
  62                 r = readl(&clk->mpll_con);
  63                 break;
  64         case EPLL:
  65                 r = readl(&clk->epll_con);
  66                 break;
  67         case HPLL:
  68                 r = readl(&clk->hpll_con);
  69                 break;
  70         default:
  71                 printf("Unsupported PLL (%d)\n", pllreg);
  72                 return 0;
  73         }
  74
  75         /*
  76          * APLL_CON: MIDV [25:16]
  77          * MPLL_CON: MIDV [23:16]
  78          * EPLL_CON: MIDV [23:16]
  79          * HPLL_CON: MIDV [23:16]
  80          */
  81         if (pllreg == APLL)
  82                 mask = 0x3ff;
  83         else
  84                 mask = 0x0ff;
  85
  86         m = (r >> 16) & mask;
  87
  88         /* PDIV [13:8] */
  89         p = (r >> 8) & 0x3f;
  90         /* SDIV [2:0] */
  91         s = r & 0x7;
  92
  93         /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
  94         freq = CONFIG_SYS_CLK_FREQ_C100;
  95         fout = m * (freq / (p * (1 << s)));
  96
  97         return fout;
  98 }
  99
 100 /* s5pc100: return pll clock frequency */
 101 static unsigned long s5pc110_get_pll_clk(int pllreg)
 102 {
 103         struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
 104         unsigned long r, m, p, s, mask, fout;
 105         unsigned int freq;
 106
 107         switch (pllreg) {
 108         case APLL:
 109                 r = readl(&clk->apll_con);
 110                 break;
 111         case MPLL:
 112                 r = readl(&clk->mpll_con);
 113                 break;
 114         case EPLL:
 115                 r = readl(&clk->epll_con);
 116                 break;
 117         case VPLL:
 118                 r = readl(&clk->vpll_con);
 119                 break;
 120         default:
 121                 printf("Unsupported PLL (%d)\n", pllreg);
 122                 return 0;
 123         }
 124
 125         /*
 126          * APLL_CON: MIDV [25:16]
 127          * MPLL_CON: MIDV [25:16]
 128          * EPLL_CON: MIDV [24:16]
 129          * VPLL_CON: MIDV [24:16]
 130          */
 131         if (pllreg == APLL || pllreg == MPLL)
 132                 mask = 0x3ff;
 133         else
 134                 mask = 0x1ff;
 135
 136         m = (r >> 16) & mask;
 137
 138         /* PDIV [13:8] */
 139         p = (r >> 8) & 0x3f;
 140         /* SDIV [2:0] */
 141         s = r & 0x7;
 142
 143         freq = CONFIG_SYS_CLK_FREQ_C110;
 144         if (pllreg == APLL) {
 145                 if (s < 1)
 146                         s = 1;
 147                 /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
 148                 fout = m * (freq / (p * (1 << (s - 1))));
 149         } else
 150                 /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
 151                 fout = m * (freq / (p * (1 << s)));
 152
 153         return fout;
 154 }
 155
 156 /* s5pc110: return ARM clock frequency */
 157 static unsigned long s5pc110_get_arm_clk(void)
 158 {
 159         struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
 160         unsigned long div;
 161         unsigned long dout_apll, armclk;
 162         unsigned int apll_ratio;
 163
 164         div = readl(&clk->div0);
 165
 166         /* APLL_RATIO: [2:0] */
 167         apll_ratio = div & 0x7;
 168
 169         dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
 170         armclk = dout_apll;
 171
 172         return armclk;
 173 }
 174
 175 /* s5pc100: return ARM clock frequency */
 176 static unsigned long s5pc100_get_arm_clk(void)
 177 {
 178         struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
 179         unsigned long div;
 180         unsigned long dout_apll, armclk;
 181         unsigned int apll_ratio, arm_ratio;
 182
 183         div = readl(&clk->div0);
 184
 185         /* ARM_RATIO: [6:4] */
 186         arm_ratio = (div >> 4) & 0x7;
 187         /* APLL_RATIO: [0] */
 188         apll_ratio = div & 0x1;
 189
 190         dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
 191         armclk = dout_apll / (arm_ratio + 1);
 192
 193         return armclk;
 194 }
 195
 196 /* s5pc100: return HCLKD0 frequency */
 197 static unsigned long get_hclk(void)
 198 {
 199         struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
 200         unsigned long hclkd0;
 201         uint div, d0_bus_ratio;
 202
 203         div = readl(&clk->div0);
 204         /* D0_BUS_RATIO: [10:8] */
 205         d0_bus_ratio = (div >> 8) & 0x7;
 206
 207         hclkd0 = get_arm_clk() / (d0_bus_ratio + 1);
 208
 209         return hclkd0;
 210 }
 211
 212 /* s5pc100: return PCLKD1 frequency */
 213 static unsigned long get_pclkd1(void)
 214 {
 215         struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
 216         unsigned long d1_bus, pclkd1;
 217         uint div, d1_bus_ratio, pclkd1_ratio;
 218
 219         div = readl(&clk->div0);
 220         /* D1_BUS_RATIO: [14:12] */
 221         d1_bus_ratio = (div >> 12) & 0x7;
 222         /* PCLKD1_RATIO: [18:16] */
 223         pclkd1_ratio = (div >> 16) & 0x7;
 224
 225         /* ASYNC Mode */
 226         d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1);
 227         pclkd1 = d1_bus / (pclkd1_ratio + 1);
 228
 229         return pclkd1;
 230 }
 231
 232 /* s5pc110: return HCLKs frequency */
 233 static unsigned long get_hclk_sys(int dom)
 234 {
 235         struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
 236         unsigned long hclk;
 237         unsigned int div;
 238         unsigned int offset;
 239         unsigned int hclk_sys_ratio;
 240
 241         if (dom == CLK_M)
 242                 return get_hclk();
 243
 244         div = readl(&clk->div0);
 245
 246         /*
 247          * HCLK_MSYS_RATIO: [10:8]
 248          * HCLK_DSYS_RATIO: [19:16]
 249          * HCLK_PSYS_RATIO: [27:24]
 250          */
 251         offset = 8 + (dom << 0x3);
 252
 253         hclk_sys_ratio = (div >> offset) & 0xf;
 254
 255         hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
 256
 257         return hclk;
 258 }
 259
 260 /* s5pc110: return PCLKs frequency */
 261 static unsigned long get_pclk_sys(int dom)
 262 {
 263         struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
 264         unsigned long pclk;
 265         unsigned int div;
 266         unsigned int offset;
 267         unsigned int pclk_sys_ratio;
 268
 269         div = readl(&clk->div0);
 270
 271         /*
 272          * PCLK_MSYS_RATIO: [14:12]
 273          * PCLK_DSYS_RATIO: [22:20]
 274          * PCLK_PSYS_RATIO: [30:28]
 275          */
 276         offset = 12 + (dom << 0x3);
 277
 278         pclk_sys_ratio = (div >> offset) & 0x7;
 279
 280         pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1);
 281
 282         return pclk;
 283 }
 284
 285 /* s5pc110: return peripheral clock frequency */
 286 static unsigned long s5pc110_get_pclk(void)
 287 {
 288         return get_pclk_sys(CLK_P);
 289 }
 290
 291 /* s5pc100: return peripheral clock frequency */
 292 static unsigned long s5pc100_get_pclk(void)
 293 {
 294         return get_pclkd1();
 295 }
 296
 297 void s5pc1xx_clock_init(void)
 298 {
 299         if (cpu_is_s5pc110()) {
 300                 get_pll_clk = s5pc110_get_pll_clk;
 301                 get_arm_clk = s5pc110_get_arm_clk;
 302                 get_pclk = s5pc110_get_pclk;
 303         } else {
 304                 get_pll_clk = s5pc100_get_pll_clk;
 305                 get_arm_clk = s5pc100_get_arm_clk;
 306                 get_pclk = s5pc100_get_pclk;
 307         }
 308 }