cpu/at91rm9200/at91rm9200_ether.c

   1 /*
   2  * (C) Copyright 2003
   3  * Author : Hamid Ikdoumi (Atmel)
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <at91rm9200_net.h>
  25 #include <net.h>
  26
  27 /* ----- Ethernet Buffer definitions ----- */
  28
  29 typedef struct {
  30         unsigned long addr, size;
  31 } rbf_t;
  32
  33 #define RBF_ADDR      0xfffffffc
  34 #define RBF_OWNER     (1<<0)
  35 #define RBF_WRAP      (1<<1)
  36 #define RBF_BROADCAST (1<<31)
  37 #define RBF_MULTICAST (1<<30)
  38 #define RBF_UNICAST   (1<<29)
  39 #define RBF_EXTERNAL  (1<<28)
  40 #define RBF_UNKOWN    (1<<27)
  41 #define RBF_SIZE      0x07ff
  42 #define RBF_LOCAL4    (1<<26)
  43 #define RBF_LOCAL3    (1<<25)
  44 #define RBF_LOCAL2    (1<<24)
  45 #define RBF_LOCAL1    (1<<23)
  46
  47 /* Emac Buffers in last 512KBytes of SDRAM*/
  48 /* Be careful, buffer size is limited to 512KBytes !!! */
  49 #define RBF_FRAMEMAX 100
  50 /*#define RBF_FRAMEMEM 0x200000 */
  51 #define RBF_FRAMEMEM 0x21F80000
  52 #define RBF_FRAMELEN 0x600
  53
  54 #define RBF_FRAMEBTD RBF_FRAMEMEM
  55 #define RBF_FRAMEBUF (RBF_FRAMEMEM + RBF_FRAMEMAX*sizeof(rbf_t))
  56
  57
  58 #ifdef CONFIG_DRIVER_ETHER
  59
  60 #if (CONFIG_COMMANDS & CFG_CMD_NET)
  61
  62 /* structure to interface the PHY */
  63 AT91S_PhyOps AT91S_Dm9161Ops;
  64 AT91PS_PhyOps pPhyOps;
  65
  66 AT91PS_EMAC p_mac;
  67
  68 /*************************** Phy layer functions ************************/
  69 /** functions to interface the DAVICOM 10/100Mbps ethernet phy **********/
  70
  71 /*
  72  * Name:
  73  *      dm9161_IsPhyConnected
  74  * Description:
  75  *      Reads the 2 PHY ID registers
  76  * Arguments:
  77  *      p_mac - pointer to AT91S_EMAC struct
  78  * Return value:
  79  *      TRUE - if id read successfully
  80  *      FALSE- if error
  81  */
  82 static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
  83 {
  84         unsigned short Id1, Id2;
  85
  86         at91rm9200_EmacEnableMDIO (p_mac);
  87         at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
  88         at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
  89         at91rm9200_EmacDisableMDIO (p_mac);
  90
  91         if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
  92                 ((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
  93                 return TRUE;
  94
  95         return FALSE;
  96 }
  97
  98 /*
  99  * Name:
 100  *      dm9161_GetLinkSpeed
 101  * Description:
 102  *      Link parallel detection status of MAC is checked and set in the
 103  *      MAC configuration registers
 104  * Arguments:
 105  *      p_mac - pointer to MAC
 106  * Return value:
 107  *      TRUE - if link status set succesfully
 108  *      FALSE - if link status not set
 109  */
 110 static UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
 111 {
 112         unsigned short stat1, stat2;
 113
 114         if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
 115                 return FALSE;
 116
 117         if (!(stat1 & DM9161_LINK_STATUS))      /* link status up? */
 118                 return FALSE;
 119
 120         if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
 121                 return FALSE;
 122
 123         if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
 124                 /*set Emac for 100BaseTX and Full Duplex  */
 125                 p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
 126                 return TRUE;
 127         }
 128
 129         if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
 130                 /*set MII for 10BaseT and Full Duplex  */
 131                 p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
 132                                 ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
 133                                 | AT91C_EMAC_FD;
 134                 return TRUE;
 135         }
 136
 137         if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) {
 138                 /*set MII for 100BaseTX and Half Duplex  */
 139                 p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
 140                                 ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
 141                                 | AT91C_EMAC_SPD;
 142                 return TRUE;
 143         }
 144
 145         if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
 146                 /*set MII for 10BaseT and Half Duplex  */
 147                 p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
 148                 return TRUE;
 149         }
 150         return FALSE;
 151 }
 152
 153
 154 /*
 155  * Name:
 156  *      dm9161_InitPhy
 157  * Description:
 158  *      MAC starts checking its link by using parallel detection and
 159  *      Autonegotiation and the same is set in the MAC configuration registers
 160  * Arguments:
 161  *      p_mac - pointer to struct AT91S_EMAC
 162  * Return value:
 163  *      TRUE - if link status set succesfully
 164  *      FALSE - if link status not set
 165  */
 166 static UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
 167 {
 168         UCHAR ret = TRUE;
 169         unsigned short IntValue;
 170
 171         at91rm9200_EmacEnableMDIO (p_mac);
 172
 173         if (!dm9161_GetLinkSpeed (p_mac)) {
 174                 /* Try another time */
 175                 ret = dm9161_GetLinkSpeed (p_mac);
 176         }
 177
 178         /* Disable PHY Interrupts */
 179         at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
 180         /* clear FDX, SPD, Link, INTR masks */
 181         IntValue &= ~(DM9161_FDX_MASK | DM9161_SPD_MASK |
 182                       DM9161_LINK_MASK | DM9161_INTR_MASK);
 183         at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
 184         at91rm9200_EmacDisableMDIO (p_mac);
 185
 186         return (ret);
 187 }
 188
 189
 190 /*
 191  * Name:
 192  *      dm9161_AutoNegotiate
 193  * Description:
 194  *      MAC Autonegotiates with the partner status of same is set in the
 195  *      MAC configuration registers
 196  * Arguments:
 197  *      dev - pointer to struct net_device
 198  * Return value:
 199  *      TRUE - if link status set successfully
 200  *      FALSE - if link status not set
 201  */
 202 static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
 203 {
 204         unsigned short value;
 205         unsigned short PhyAnar;
 206         unsigned short PhyAnalpar;
 207
 208         /* Set dm9161 control register */
 209         if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
 210                 return FALSE;
 211         value &= ~DM9161_AUTONEG;       /* remove autonegotiation enable */
 212         value |= DM9161_ISOLATE;        /* Electrically isolate PHY */
 213         if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
 214                 return FALSE;
 215
 216         /* Set the Auto_negotiation Advertisement Register */
 217         /* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
 218         PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
 219                   DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
 220         if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
 221                 return FALSE;
 222
 223         /* Read the Control Register     */
 224         if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
 225                 return FALSE;
 226
 227         value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
 228         if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
 229                 return FALSE;
 230         /* Restart Auto_negotiation  */
 231         value |= DM9161_RESTART_AUTONEG;
 232         if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
 233                 return FALSE;
 234
 235         /*check AutoNegotiate complete */
 236         udelay (10000);
 237         at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
 238         if (!(value & DM9161_AUTONEG_COMP))
 239                 return FALSE;
 240
 241         /* Get the AutoNeg Link partner base page */
 242         if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
 243                 return FALSE;
 244
 245         if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
 246                 /*set MII for 100BaseTX and Full Duplex  */
 247                 p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
 248                 return TRUE;
 249         }
 250
 251         if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
 252                 /*set MII for 10BaseT and Full Duplex  */
 253                 p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
 254                                 ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
 255                                 | AT91C_EMAC_FD;
 256                 return TRUE;
 257         }
 258         return FALSE;
 259 }
 260
 261
 262 /*********** EMAC Phy layer Management functions *************************/
 263 /*
 264  * Name:
 265  *      at91rm9200_EmacEnableMDIO
 266  * Description:
 267  *      Enables the MDIO bit in MAC control register
 268  * Arguments:
 269  *      p_mac - pointer to struct AT91S_EMAC
 270  * Return value:
 271  *      none
 272  */
 273 static void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
 274 {
 275         /* Mac CTRL reg set for MDIO enable */
 276         p_mac->EMAC_CTL |= AT91C_EMAC_MPE;      /* Management port enable */
 277 }
 278
 279 /*
 280  * Name:
 281  *      at91rm9200_EmacDisableMDIO
 282  * Description:
 283  *      Disables the MDIO bit in MAC control register
 284  * Arguments:
 285  *      p_mac - pointer to struct AT91S_EMAC
 286  * Return value:
 287  *      none
 288  */
 289 static void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
 290 {
 291         /* Mac CTRL reg set for MDIO disable */
 292         p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE;     /* Management port disable */
 293 }
 294
 295
 296 /*
 297  * Name:
 298  *      at91rm9200_EmacReadPhy
 299  * Description:
 300  *      Reads data from the PHY register
 301  * Arguments:
 302  *      dev - pointer to struct net_device
 303  *      RegisterAddress - unsigned char
 304  *      pInput - pointer to value read from register
 305  * Return value:
 306  *      TRUE - if data read successfully
 307  */
 308 static UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
 309                                      unsigned char RegisterAddress,
 310                                      unsigned short *pInput)
 311 {
 312         p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
 313                           (AT91C_EMAC_RW_R) |
 314                           (RegisterAddress << 18) |
 315                           (AT91C_EMAC_CODE_802_3);
 316
 317         udelay (10000);
 318
 319         *pInput = (unsigned short) p_mac->EMAC_MAN;
 320
 321         return TRUE;
 322 }
 323
 324
 325 /*
 326  * Name:
 327  *      at91rm9200_EmacWritePhy
 328  * Description:
 329  *      Writes data to the PHY register
 330  * Arguments:
 331  *      dev - pointer to struct net_device
 332  *      RegisterAddress - unsigned char
 333  *      pOutput - pointer to value to be written in the register
 334  * Return value:
 335  *      TRUE - if data read successfully
 336  */
 337 static UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
 338                                       unsigned char RegisterAddress,
 339                                       unsigned short *pOutput)
 340 {
 341         p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
 342                         AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W |
 343                         (RegisterAddress << 18) | *pOutput;
 344
 345         udelay (10000);
 346
 347         return TRUE;
 348 }
 349
 350 /*
 351  * Name:
 352  *      at91rm92000_GetPhyInterface
 353  * Description:
 354  *      Initialise the interface functions to the PHY
 355  * Arguments:
 356  *      None
 357  * Return value:
 358  *      None
 359  */
 360 void at91rm92000_GetPhyInterface (void)
 361 {
 362         AT91S_Dm9161Ops.Init = dm9161_InitPhy;
 363         AT91S_Dm9161Ops.IsPhyConnected = dm9161_IsPhyConnected;
 364         AT91S_Dm9161Ops.GetLinkSpeed = dm9161_GetLinkSpeed;
 365         AT91S_Dm9161Ops.AutoNegotiate = dm9161_AutoNegotiate;
 366
 367         pPhyOps = (AT91PS_PhyOps) & AT91S_Dm9161Ops;
 368 }
 369
 370
 371 rbf_t *rbfdt;
 372 rbf_t *rbfp;
 373
 374 int eth_init (bd_t * bd)
 375 {
 376         int ret;
 377         int i;
 378
 379         p_mac = AT91C_BASE_EMAC;
 380
 381         /* PIO Disable Register */
 382         *AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER |
 383                           AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV |
 384                           AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
 385                           AT91C_PA7_ETXCK_EREFCK;
 386
 387         *AT91C_PIOB_PDR = AT91C_PB25_EF100 |
 388                           AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
 389                           AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
 390                           AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
 391
 392         /* Select B Register */
 393         *AT91C_PIOB_BSR = AT91C_PB25_EF100 | AT91C_PB19_ERXCK | AT91C_PB18_ECOL |
 394                           AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 |
 395                           AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
 396
 397         *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC;   /* Peripheral Clock Enable Register */
 398
 399         p_mac->EMAC_CFG |= AT91C_EMAC_CSR;      /* Clear statistics */
 400
 401         /* Init Ehternet buffers */
 402         rbfdt = (rbf_t *) RBF_FRAMEBTD;
 403         for (i = 0; i < RBF_FRAMEMAX; i++) {
 404                 rbfdt[i].addr = RBF_FRAMEBUF + RBF_FRAMELEN * i;
 405                 rbfdt[i].size = 0;
 406         }
 407         rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
 408         rbfp = &rbfdt[0];
 409
 410         p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16)
 411                          | (bd->bi_enetaddr[1] <<  8) | (bd->bi_enetaddr[0]);
 412         p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] <<  8) | (bd->bi_enetaddr[4]);
 413
 414         p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
 415         p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
 416
 417         p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
 418                         & ~AT91C_EMAC_CLK;
 419
 420 #ifdef CONFIG_AT91C_USE_RMII
 421         p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
 422 #endif
 423
 424         p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
 425
 426         at91rm92000_GetPhyInterface ();
 427
 428         if (!pPhyOps->IsPhyConnected (p_mac))
 429                 printf ("PHY not connected!!\n\r");
 430
 431         /* MII management start from here */
 432         if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) {
 433                 if (!(ret = pPhyOps->Init (p_mac))) {
 434                         printf ("MAC: error during MII initialization\n");
 435                         return 0;
 436                 }
 437         } else {
 438                 printf ("No link\n\r");
 439                 return 0;
 440         }
 441
 442         return 0;
 443 }
 444
 445 int eth_send (volatile void *packet, int length)
 446 {
 447         while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ));
 448         p_mac->EMAC_TAR = (long) packet;
 449         p_mac->EMAC_TCR = length;
 450         while (p_mac->EMAC_TCR & 0x7ff);
 451         p_mac->EMAC_TSR |= AT91C_EMAC_COMP;
 452         return 0;
 453 }
 454
 455 int eth_rx (void)
 456 {
 457         int size;
 458
 459         if (!(rbfp->addr & RBF_OWNER))
 460                 return 0;
 461
 462         size = rbfp->size & RBF_SIZE;
 463         NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
 464
 465         rbfp->addr &= ~RBF_OWNER;
 466         if (rbfp->addr & RBF_WRAP)
 467                 rbfp = &rbfdt[0];
 468         else
 469                 rbfp++;
 470
 471         p_mac->EMAC_RSR |= AT91C_EMAC_REC;
 472
 473         return size;
 474 }
 475
 476 void eth_halt (void)
 477 {
 478 };
 479
 480 #if (CONFIG_COMMANDS & CFG_CMD_MII)
 481 int  miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
 482 {
 483         at91rm9200_EmacEnableMDIO (p_mac);
 484         at91rm9200_EmacReadPhy (p_mac, reg, value);
 485         at91rm9200_EmacDisableMDIO (p_mac);
 486         return 0;
 487 }
 488
 489 int  miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
 490 {
 491         at91rm9200_EmacEnableMDIO (p_mac);
 492         at91rm9200_EmacWritePhy (p_mac, reg, &value);
 493         at91rm9200_EmacDisableMDIO (p_mac);
 494         return 0;
 495 }
 496 #endif  /* CONFIG_COMMANDS & CFG_CMD_MII */
 497
 498 #endif  /* CONFIG_COMMANDS & CFG_CMD_NET */
 499
 500 #endif  /* CONFIG_DRIVER_ETHER */