cpu/at91rm9200/cpu.c

   1 /*
   2  * (C) Copyright 2002
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Marius Groeger <mgroeger@sysgo.de>
   5  *
   6  * (C) Copyright 2002
   7  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   8  * Alex Zuepke <azu@sysgo.de>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /*
  30  * CPU specific code
  31  */
  32
  33 #include <common.h>
  34 #include <command.h>
  35 #include <asm/io.h>
  36 #include <asm/arch/hardware.h>
  37
  38 /* read co-processor 15, register #1 (control register) */
  39 static unsigned long read_p15_c1(void)
  40 {
  41     unsigned long value;
  42
  43     __asm__ __volatile__(
  44         "mrc     p15, 0, %0, c1, c0, 0   @ read control reg\n"
  45         : "=r" (value)
  46         :
  47         : "memory");
  48     /*printf("p15/c1 is = %08lx\n", value); */
  49     return value;
  50 }
  51
  52 /* write to co-processor 15, register #1 (control register) */
  53 static void write_p15_c1(unsigned long value)
  54 {
  55     /*printf("write %08lx to p15/c1\n", value); */
  56     __asm__ __volatile__(
  57         "mcr     p15, 0, %0, c1, c0, 0   @ write it back\n"
  58         : "=r" (value)
  59         :
  60         : "memory");
  61
  62     read_p15_c1();
  63 }
  64
  65 static void cp_delay(void)
  66 {
  67     volatile int i;
  68
  69     /* copro seems to need some delay between reading and writing */
  70     for (i=0; i<100; i++);
  71 }
  72 /* See also ARM Ref. Man. */
  73 #define C1_MMU          (1<<0)  /* mmu off/on */
  74 #define C1_ALIGN        (1<<1)  /* alignment faults off/on */
  75 #define C1_IDC          (1<<2)  /* icache and/or dcache off/on */
  76 #define C1_WRITE_BUFFER (1<<3)  /* write buffer off/on */
  77 #define C1_BIG_ENDIAN   (1<<7)  /* big endian off/on */
  78 #define C1_SYS_PROT     (1<<8)  /* system protection */
  79 #define C1_ROM_PROT     (1<<9)  /* ROM protection */
  80 #define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
  81
  82 int cpu_init(void)
  83 {
  84     /*
  85      * setup up stack if necessary
  86      */
  87 #ifdef CONFIG_USE_IRQ
  88     IRQ_STACK_START = _armboot_end +
  89                         CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
  90     FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
  91     _armboot_real_end = FIQ_STACK_START + 4;
  92 #else
  93     _armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
  94 #endif
  95     return 0;
  96 }
  97
  98 int cleanup_before_linux(void)
  99 {
 100     /*
 101      * this function is called just before we call linux
 102      * it prepares the processor for linux
 103      *
 104      * we turn off caches etc ...
 105      * and we set the CPU-speed to 73 MHz - see start.S for details
 106      */
 107
 108     disable_interrupts();
 109     return 0;
 110 }
 111
 112 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 113 {
 114
 115 #ifdef CFG_SOFT_RESET
 116     extern void reset_cpu(ulong addr);
 117
 118     disable_interrupts();
 119     reset_cpu(0);
 120 #else
 121    AT91PS_USART us = AT91C_BASE_US1;
 122    AT91PS_PIO pio = AT91C_BASE_PIOA;
 123
 124    /*shutdown the console to avoid strange chars during reset */
 125    us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
 126
 127    /* Clear PA19 to trigger the hard reset */
 128    pio->PIO_CODR = 0x00080000;
 129    pio->PIO_OER  = 0x00080000;
 130    pio->PIO_PER  = 0x00080000;
 131    /* Never reached */
 132 #endif
 133    return 0;
 134 }
 135
 136 void icache_enable(void)
 137 {
 138     ulong reg;
 139     reg = read_p15_c1();
 140     cp_delay();
 141     write_p15_c1(reg | C1_IDC);
 142 }
 143
 144 void icache_disable(void)
 145 {
 146     ulong reg;
 147     reg = read_p15_c1();
 148     cp_delay();
 149     write_p15_c1(reg & ~C1_IDC);
 150 }
 151
 152 int icache_status(void)
 153 {
 154     return (read_p15_c1() & C1_IDC) != 0;
 155     return 0;
 156 }
 157
 158 void dcache_enable(void)
 159 {
 160     ulong reg;
 161     reg = read_p15_c1();
 162     cp_delay();
 163     write_p15_c1(reg | C1_IDC);
 164 }
 165
 166 void dcache_disable(void)
 167 {
 168     ulong reg;
 169     reg = read_p15_c1();
 170     cp_delay();
 171     write_p15_c1(reg & ~C1_IDC);
 172 }
 173
 174 int dcache_status(void)
 175 {
 176     return (read_p15_c1() & C1_IDC) != 0;
 177     return 0;
 178 }