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* Patch by Daniel Engström, 13 Nov 2002:
[people/ms/u-boot.git] / cpu / i386 / interrupts.c
1 /*
2 * (C) Copyright 2002
3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25 #include <syscall.h>
26 #include <malloc.h>
27 #include <asm/io.h>
28 #include <asm/i8259.h>
29 #include <asm/ibmpc.h>
30
31
32 #if 0
33 /* done */
34 int interrupt_init (void);
35 void irq_install_handler(int, interrupt_handler_t *, void *);
36 void irq_free_handler (int);
37 void enable_interrupts (void);
38 int disable_interrupts (void);
39
40 /* todo */
41 void timer_interrupt (struct pt_regs *);
42 void external_interrupt (struct pt_regs *);
43 void reset_timer (void);
44 ulong get_timer (ulong base);
45 void set_timer (ulong t);
46
47 #endif
48
49 struct idt_entry {
50 u16 base_low;
51 u16 selector;
52 u8 res;
53 u8 access;
54 u16 base_high;
55 } __attribute__ ((packed));
56
57
58 struct idt_entry idt[256];
59
60
61 #define MAX_IRQ 16
62
63 typedef struct irq_handler {
64 struct irq_handler *next;
65 interrupt_handler_t* isr_func;
66 void *isr_data;
67 } irq_handler_t;
68
69 #define IRQ_DISABLED 1
70
71 typedef struct {
72 irq_handler_t *handler;
73 unsigned long status;
74 } irq_desc_t;
75
76 static irq_desc_t irq_table[MAX_IRQ];
77
78
79 /* syscall stuff, very untested
80 * the current approach which includes copying
81 * part of the stack will work badly for
82 * varargs functions.
83 * if we were to store the top three words on the
84 * stack (eip, ss, eflags) somwhere and add 14 to
85 * %esp ....
86 */
87 asm(".globl syscall_entry\n" \
88 "syscall_entry:\n" \
89 "movl 12(%esp), %eax\n" \
90 "movl %esp, %ebx\n" \
91 "addl $16, %ebx\n" \
92 "pushl %ebx\n" \
93 "pushl %eax\n" \
94 "call do_syscall\n" \
95 "addl $8, %esp\n" \
96 "iret\n");
97
98 void __attribute__ ((regparm(0))) syscall_entry(void);
99
100 int __attribute__ ((regparm(0))) do_syscall(u32 nr, u32 *stack)
101 {
102 if (nr<NR_SYSCALLS) {
103 /* We copy 8 args of the syscall,
104 * this will be a problem with the
105 * printf syscall .... */
106 int (*fp)(u32, u32, u32, u32,
107 u32, u32, u32, u32);
108 fp = syscall_tbl[nr];
109 return fp(stack[0], stack[1], stack[2], stack[3],
110 stack[4], stack[5], stack[6], stack[7]);
111 }
112
113 return -1;
114 }
115
116
117 asm ("irq_return:\n"
118 " addl $4, %esp\n"
119 " popa\n"
120 " iret\n");
121
122 asm ("exp_return:\n"
123 " addl $12, %esp\n"
124 " pop %esp\n"
125 " popa\n"
126 " iret\n");
127
128 char exception_stack[4096];
129
130 #define DECLARE_INTERRUPT(x) \
131 asm(".globl irq_"#x"\n" \
132 "irq_"#x":\n" \
133 "pusha \n" \
134 "pushl $"#x"\n" \
135 "pushl $irq_return\n" \
136 "jmp do_irq\n"); \
137 void __attribute__ ((regparm(0))) irq_##x(void)
138
139 #define DECLARE_EXCEPTION(x, f) \
140 asm(".globl exp_"#x"\n" \
141 "exp_"#x":\n" \
142 "pusha \n" \
143 "movl %esp, %ebx\n" \
144 "movl $exception_stack, %eax\n" \
145 "movl %eax, %esp \n" \
146 "pushl %ebx\n" \
147 "movl 32(%esp), %ebx\n" \
148 "xorl %edx, %edx\n" \
149 "movw 36(%esp), %dx\n" \
150 "pushl %edx\n" \
151 "pushl %ebx\n" \
152 "pushl $"#x"\n" \
153 "pushl $exp_return\n" \
154 "jmp "#f"\n"); \
155 void __attribute__ ((regparm(0))) exp_##x(void)
156
157 DECLARE_EXCEPTION(0, divide_exception_entry); /* Divide exception */
158 DECLARE_EXCEPTION(1, debug_exception_entry); /* Debug exception */
159 DECLARE_EXCEPTION(2, nmi_entry); /* NMI */
160 DECLARE_EXCEPTION(3, unknown_exception_entry); /* Breakpoint/Coprocessor Error */
161 DECLARE_EXCEPTION(4, unknown_exception_entry); /* Overflow */
162 DECLARE_EXCEPTION(5, unknown_exception_entry); /* Bounds */
163 DECLARE_EXCEPTION(6, invalid_instruction_entry); /* Invalid instruction */
164 DECLARE_EXCEPTION(7, unknown_exception_entry); /* Device not present */
165 DECLARE_EXCEPTION(8, double_fault_entry); /* Double fault */
166 DECLARE_EXCEPTION(9, unknown_exception_entry); /* Co-processor segment overrun */
167 DECLARE_EXCEPTION(10, invalid_tss_exception_entry);/* Invalid TSS */
168 DECLARE_EXCEPTION(11, seg_fault_entry); /* Segment not present */
169 DECLARE_EXCEPTION(12, stack_fault_entry); /* Stack overflow */
170 DECLARE_EXCEPTION(13, gpf_entry); /* GPF */
171 DECLARE_EXCEPTION(14, page_fault_entry); /* PF */
172 DECLARE_EXCEPTION(15, unknown_exception_entry); /* Reserved */
173 DECLARE_EXCEPTION(16, fp_exception_entry); /* Floating point */
174 DECLARE_EXCEPTION(17, alignment_check_entry); /* alignment check */
175 DECLARE_EXCEPTION(18, machine_check_entry); /* machine check */
176 DECLARE_EXCEPTION(19, unknown_exception_entry); /* Reserved */
177 DECLARE_EXCEPTION(20, unknown_exception_entry); /* Reserved */
178 DECLARE_EXCEPTION(21, unknown_exception_entry); /* Reserved */
179 DECLARE_EXCEPTION(22, unknown_exception_entry); /* Reserved */
180 DECLARE_EXCEPTION(23, unknown_exception_entry); /* Reserved */
181 DECLARE_EXCEPTION(24, unknown_exception_entry); /* Reserved */
182 DECLARE_EXCEPTION(25, unknown_exception_entry); /* Reserved */
183 DECLARE_EXCEPTION(26, unknown_exception_entry); /* Reserved */
184 DECLARE_EXCEPTION(27, unknown_exception_entry); /* Reserved */
185 DECLARE_EXCEPTION(28, unknown_exception_entry); /* Reserved */
186 DECLARE_EXCEPTION(29, unknown_exception_entry); /* Reserved */
187 DECLARE_EXCEPTION(30, unknown_exception_entry); /* Reserved */
188 DECLARE_EXCEPTION(31, unknown_exception_entry); /* Reserved */
189
190 DECLARE_INTERRUPT(0);
191 DECLARE_INTERRUPT(1);
192 DECLARE_INTERRUPT(3);
193 DECLARE_INTERRUPT(4);
194 DECLARE_INTERRUPT(5);
195 DECLARE_INTERRUPT(6);
196 DECLARE_INTERRUPT(7);
197 DECLARE_INTERRUPT(8);
198 DECLARE_INTERRUPT(9);
199 DECLARE_INTERRUPT(10);
200 DECLARE_INTERRUPT(11);
201 DECLARE_INTERRUPT(12);
202 DECLARE_INTERRUPT(13);
203 DECLARE_INTERRUPT(14);
204 DECLARE_INTERRUPT(15);
205
206 void __attribute__ ((regparm(0))) default_isr(void);
207 asm ("default_isr: iret\n");
208
209 void disable_irq(int irq)
210 {
211 if (irq >= MAX_IRQ) {
212 return;
213 }
214 irq_table[irq].status |= IRQ_DISABLED;
215
216 }
217
218 void enable_irq(int irq)
219 {
220 if (irq >= MAX_IRQ) {
221 return;
222 }
223 irq_table[irq].status &= ~IRQ_DISABLED;
224 }
225
226 /* masks one specific IRQ in the PIC */
227 static void unmask_irq(int irq)
228 {
229 int imr_port;
230
231 if (irq >= MAX_IRQ) {
232 return;
233 }
234 if (irq > 7) {
235 imr_port = SLAVE_PIC + IMR;
236 } else {
237 imr_port = MASTER_PIC + IMR;
238 }
239
240 outb(inb(imr_port)&~(1<<(irq&7)), imr_port);
241 }
242
243
244 /* unmasks one specific IRQ in the PIC */
245 static void mask_irq(int irq)
246 {
247 int imr_port;
248
249 if (irq >= MAX_IRQ) {
250 return;
251 }
252 if (irq > 7) {
253 imr_port = SLAVE_PIC + IMR;
254 } else {
255 imr_port = MASTER_PIC + IMR;
256 }
257
258 outb(inb(imr_port)|(1<<(irq&7)), imr_port);
259 }
260
261
262 /* issue a Specific End Of Interrupt instruciton */
263 static void specific_eoi(int irq)
264 {
265 /* If it is on the slave PIC this have to be performed on
266 * both the master and the slave PICs */
267 if (irq > 7) {
268 outb(OCW2_SEOI|(irq&7), SLAVE_PIC + OCW2);
269 irq = SEOI_IR2; /* also do IR2 on master */
270 }
271 outb(OCW2_SEOI|irq, MASTER_PIC + OCW2);
272 }
273
274 void __attribute__ ((regparm(0))) do_irq(int irq)
275 {
276
277 mask_irq(irq);
278
279 if (irq_table[irq].status & IRQ_DISABLED) {
280 unmask_irq(irq);
281 specific_eoi(irq);
282 return;
283 }
284
285
286 if (NULL != irq_table[irq].handler) {
287 irq_handler_t *handler;
288 for (handler = irq_table[irq].handler;
289 NULL!= handler; handler = handler->next) {
290 handler->isr_func(handler->isr_data);
291 }
292 } else {
293 if ((irq & 7) != 7) {
294 printf("Spurious irq %d\n", irq);
295 }
296 }
297 unmask_irq(irq);
298 specific_eoi(irq);
299 }
300
301
302 void __attribute__ ((regparm(0))) unknown_exception_entry(int cause, int ip, int seg)
303 {
304 printf("Unknown Exception %d at %04x:%08x\n", cause, seg, ip);
305 }
306
307 void __attribute__ ((regparm(0))) divide_exception_entry(int cause, int ip, int seg)
308 {
309 printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip);
310 while(1);
311 }
312
313 void __attribute__ ((regparm(0))) debug_exception_entry(int cause, int ip, int seg)
314 {
315 printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip);
316 }
317
318 void __attribute__ ((regparm(0))) nmi_entry(int cause, int ip, int seg)
319 {
320 printf("NMI Interrupt at %04x:%08x\n", seg, ip);
321 }
322
323 void __attribute__ ((regparm(0))) invalid_instruction_entry(int cause, int ip, int seg)
324 {
325 printf("Invalid Instruction at %04x:%08x\n", seg, ip);
326 while(1);
327 }
328
329 void __attribute__ ((regparm(0))) double_fault_entry(int cause, int ip, int seg)
330 {
331 printf("Double fault at %04x:%08x\n", seg, ip);
332 while(1);
333 }
334
335 void __attribute__ ((regparm(0))) invalid_tss_exception_entry(int cause, int ip, int seg)
336 {
337 printf("Invalid TSS at %04x:%08x\n", seg, ip);
338 }
339
340 void __attribute__ ((regparm(0))) seg_fault_entry(int cause, int ip, int seg)
341 {
342 printf("Segmentation fault at %04x:%08x\n", seg, ip);
343 while(1);
344 }
345
346 void __attribute__ ((regparm(0))) stack_fault_entry(int cause, int ip, int seg)
347 {
348 printf("Stack fault at %04x:%08x\n", seg, ip);
349 while(1);
350 }
351
352 void __attribute__ ((regparm(0))) gpf_entry(int cause, int ip, int seg)
353 {
354 printf("General protection fault at %04x:%08x\n", seg, ip);
355 }
356
357 void __attribute__ ((regparm(0))) page_fault_entry(int cause, int ip, int seg)
358 {
359 printf("Page fault at %04x:%08x\n", seg, ip);
360 while(1);
361 }
362
363 void __attribute__ ((regparm(0))) fp_exception_entry(int cause, int ip, int seg)
364 {
365 printf("Floating point exception at %04x:%08x\n", seg, ip);
366 }
367
368 void __attribute__ ((regparm(0))) alignment_check_entry(int cause, int ip, int seg)
369 {
370 printf("Alignment check at %04x:%08x\n", seg, ip);
371 }
372
373 void __attribute__ ((regparm(0))) machine_check_entry(int cause, int ip, int seg)
374 {
375 printf("Machine check exception at %04x:%08x\n", seg, ip);
376 }
377
378
379 void irq_install_handler(int ino, interrupt_handler_t *func, void *pdata)
380 {
381 int status;
382
383 if (ino>MAX_IRQ) {
384 return;
385 }
386
387 if (NULL != irq_table[ino].handler) {
388 return;
389 }
390
391 status = disable_interrupts();
392 irq_table[ino].handler = malloc(sizeof(irq_handler_t));
393 if (NULL == irq_table[ino].handler) {
394 return;
395 }
396
397 memset(irq_table[ino].handler, 0, sizeof(irq_handler_t));
398
399 irq_table[ino].handler->isr_func = func;
400 irq_table[ino].handler->isr_data = pdata;
401 if (status) {
402 enable_interrupts();
403 }
404
405 unmask_irq(ino);
406
407 return;
408 }
409
410 void irq_free_handler(int ino)
411 {
412 int status;
413 if (ino>MAX_IRQ) {
414 return;
415 }
416
417 status = disable_interrupts();
418 mask_irq(ino);
419 if (NULL == irq_table[ino].handler) {
420 return;
421 }
422 free(irq_table[ino].handler);
423 irq_table[ino].handler=NULL;
424 if (status) {
425 enable_interrupts();
426 }
427 return;
428 }
429
430
431 asm ("idt_ptr:\n"
432 ".word 0x800\n" /* size of the table 8*256 bytes */
433 ".long idt\n" /* offset */
434 ".word 0x18\n");/* data segment */
435
436 static void set_vector(int intnum, void *routine)
437 {
438 idt[intnum].base_high = (u16)((u32)(routine)>>16);
439 idt[intnum].base_low = (u16)((u32)(routine)&0xffff);
440 }
441
442
443 int interrupt_init(void)
444 {
445 int i;
446
447 /* Just in case... */
448 disable_interrupts();
449
450 /* Initialize the IDT and stuff */
451
452
453 memset(irq_table, 0, sizeof(irq_table));
454
455 /* Setup the IDT */
456 for (i=0;i<256;i++) {
457 idt[i].access = 0x8e;
458 idt[i].res = 0;
459 idt[i].selector = 0x10;
460 set_vector(i, default_isr);
461 }
462
463 asm ("cs lidt idt_ptr\n");
464
465 /* Setup exceptions */
466 set_vector(0x00, exp_0);
467 set_vector(0x01, exp_1);
468 set_vector(0x02, exp_2);
469 set_vector(0x03, exp_3);
470 set_vector(0x04, exp_4);
471 set_vector(0x05, exp_5);
472 set_vector(0x06, exp_6);
473 set_vector(0x07, exp_7);
474 set_vector(0x08, exp_8);
475 set_vector(0x09, exp_9);
476 set_vector(0x0a, exp_10);
477 set_vector(0x0b, exp_11);
478 set_vector(0x0c, exp_12);
479 set_vector(0x0d, exp_13);
480 set_vector(0x0e, exp_14);
481 set_vector(0x0f, exp_15);
482 set_vector(0x10, exp_16);
483 set_vector(0x11, exp_17);
484 set_vector(0x12, exp_18);
485 set_vector(0x13, exp_19);
486 set_vector(0x14, exp_20);
487 set_vector(0x15, exp_21);
488 set_vector(0x16, exp_22);
489 set_vector(0x17, exp_23);
490 set_vector(0x18, exp_24);
491 set_vector(0x19, exp_25);
492 set_vector(0x1a, exp_26);
493 set_vector(0x1b, exp_27);
494 set_vector(0x1c, exp_28);
495 set_vector(0x1d, exp_29);
496 set_vector(0x1e, exp_30);
497 set_vector(0x1f, exp_31);
498
499
500 /* Setup interrupts */
501 set_vector(0x20, irq_0);
502 set_vector(0x21, irq_1);
503 set_vector(0x23, irq_3);
504 set_vector(0x24, irq_4);
505 set_vector(0x25, irq_5);
506 set_vector(0x26, irq_6);
507 set_vector(0x27, irq_7);
508 set_vector(0x28, irq_8);
509 set_vector(0x29, irq_9);
510 set_vector(0x2a, irq_10);
511 set_vector(0x2b, irq_11);
512 set_vector(0x2c, irq_12);
513 set_vector(0x2d, irq_13);
514 set_vector(0x2e, irq_14);
515 set_vector(0x2f, irq_15);
516 /* vectors 0x30-0x3f are reserved for irq 16-31 */
517 set_vector(0x40, syscall_entry);
518
519
520 /* Mask all interrupts */
521 outb(0xff, MASTER_PIC + IMR);
522 outb(0xff, SLAVE_PIC + IMR);
523
524 /* Master PIC */
525 outb(ICW1_SEL|ICW1_EICW4, MASTER_PIC + ICW1);
526 outb(0x20, MASTER_PIC + ICW2); /* Place master PIC interrupts at INT20 */
527 outb(IR2, MASTER_PIC + ICW3); /* ICW3, One slevc PIC is present */
528 outb(ICW4_PM, MASTER_PIC + ICW4);
529
530 for (i=0;i<8;i++) {
531 outb(OCW2_SEOI|i, MASTER_PIC + OCW2);
532 }
533
534 /* Slave PIC */
535 outb(ICW1_SEL|ICW1_EICW4, SLAVE_PIC + ICW1);
536 outb(0x28, SLAVE_PIC + ICW2); /* Place slave PIC interrupts at INT28 */
537 outb(0x02, SLAVE_PIC + ICW3); /* Slave ID */
538 outb(ICW4_PM, SLAVE_PIC + ICW4);
539
540 for (i=0;i<8;i++) {
541 outb(OCW2_SEOI|i, SLAVE_PIC + OCW2);
542 }
543
544
545 /* enable cascade interrerupt */
546 outb(0xfb, MASTER_PIC + IMR);
547 outb(0xff, SLAVE_PIC + IMR);
548
549 /* It is now safe to enable interrupts */
550 enable_interrupts();
551
552 return 0;
553 }
554
555 void enable_interrupts(void)
556 {
557 asm("sti\n");
558 }
559
560 int disable_interrupts(void)
561 {
562 long flags;
563
564 asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
565
566 return (flags&0x200); /* IE flags is bit 9 */
567 }
568
569
570 #ifdef CFG_RESET_GENERIC
571
572 void __attribute__ ((regparm(0))) generate_gpf(void);
573 asm(".globl generate_gpf\n"
574 "generate_gpf:\n"
575 "ljmp $0x70, $0x47114711\n"); /* segment 0x70 is an arbitrary segment which does not
576 * exist */
577 void reset_cpu(ulong addr)
578 {
579 set_vector(13, generate_gpf); /* general protection fault handler */
580 set_vector(8, generate_gpf); /* double fault handler */
581 generate_gpf(); /* start the show */
582 }
583 #endif
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