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* Code cleanup:
[u-boot.git] / cpu / i386 / sc520.c
1 /*
2 * (C) Copyright 2002
3 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /* stuff specific for the sc520,
25 * but idependent of implementation */
26
27 #include <config.h>
28
29 #ifdef CONFIG_SC520
30
31 #include <common.h>
32 #include <config.h>
33 #include <pci.h>
34 #include <ssi.h>
35 #include <asm/io.h>
36 #include <asm/pci.h>
37 #include <asm/ic/sc520.h>
38
39 /*
40 * utility functions for boards based on the AMD sc520
41 *
42 * void write_mmcr_byte(u16 mmcr, u8 data)
43 * void write_mmcr_word(u16 mmcr, u16 data)
44 * void write_mmcr_long(u16 mmcr, u32 data)
45 *
46 * u8 read_mmcr_byte(u16 mmcr)
47 * u16 read_mmcr_word(u16 mmcr)
48 * u32 read_mmcr_long(u16 mmcr)
49 *
50 * void init_sc520(void)
51 * unsigned long init_sc520_dram(void)
52 * void pci_sc520_init(struct pci_controller *hose)
53 *
54 * void reset_timer(void)
55 * ulong get_timer(ulong base)
56 * void set_timer(ulong t)
57 * void udelay(unsigned long usec)
58 *
59 */
60
61 static u32 mmcr_base= 0xfffef000;
62
63 void write_mmcr_byte(u16 mmcr, u8 data)
64 {
65 writeb(data, mmcr+mmcr_base);
66 }
67
68 void write_mmcr_word(u16 mmcr, u16 data)
69 {
70 writew(data, mmcr+mmcr_base);
71 }
72
73 void write_mmcr_long(u16 mmcr, u32 data)
74 {
75 writel(data, mmcr+mmcr_base);
76 }
77
78 u8 read_mmcr_byte(u16 mmcr)
79 {
80 return readb(mmcr+mmcr_base);
81 }
82
83 u16 read_mmcr_word(u16 mmcr)
84 {
85 return readw(mmcr+mmcr_base);
86 }
87
88 u32 read_mmcr_long(u16 mmcr)
89 {
90 return readl(mmcr+mmcr_base);
91 }
92
93
94 void init_sc520(void)
95 {
96 DECLARE_GLOBAL_DATA_PTR;
97
98 /* Set the UARTxCTL register at it's slower,
99 * baud clock giving us a 1.8432 MHz reference
100 */
101 write_mmcr_byte(SC520_UART1CTL, 7);
102 write_mmcr_byte(SC520_UART2CTL, 7);
103
104 /* first set the timer pin mapping */
105 write_mmcr_byte(SC520_CLKSEL, 0x72); /* no clock frequency selected, use 1.1892MHz */
106
107 /* enable PCI bus arbitrer */
108 write_mmcr_byte(SC520_SYSARBCTL,0x02); /* enable concurrent mode */
109
110 write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */
111 write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */
112
113
114 if (CFG_SC520_HIGH_SPEED) {
115 write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */
116 gd->cpu_clk = 133000000;
117 printf("## CPU Speed set to 133MHz\n");
118 } else {
119 write_mmcr_byte(SC520_CPUCTL, 1); /* set CPU to 100 MHz and write back cache */
120 printf("## CPU Speed set to 100MHz\n");
121 gd->cpu_clk = 100000000;
122 }
123
124
125 /* wait at least one millisecond */
126 asm("movl $0x2000,%%ecx\n"
127 "wait_loop: pushl %%ecx\n"
128 "popl %%ecx\n"
129 "loop wait_loop\n": : : "ecx");
130
131 /* turn on the SDRAM write buffer */
132 write_mmcr_byte(SC520_DBCTL, 0x11);
133
134 /* turn on the cache and disable write through */
135 asm("movl %%cr0, %%eax\n"
136 "andl $0x9fffffff, %%eax\n"
137 "movl %%eax, %%cr0\n" : : : "eax");
138 }
139
140 unsigned long init_sc520_dram(void)
141 {
142 DECLARE_GLOBAL_DATA_PTR;
143 bd_t *bd = gd->bd;
144
145 u32 dram_present=0;
146 u32 dram_ctrl;
147
148 int val;
149
150 int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;
151 int refresh_rate = CFG_SDRAM_REFRESH_RATE;
152 int ras_cas_delay = CFG_SDRAM_RAS_CAS_DELAY;
153
154 /* set SDRAM speed here */
155
156 refresh_rate/=78;
157 if (refresh_rate<=1) {
158 val = 0; /* 7.8us */
159 } else if (refresh_rate==2) {
160 val = 1; /* 15.6us */
161 } else if (refresh_rate==3 || refresh_rate==4) {
162 val = 2; /* 31.2us */
163 } else {
164 val = 3; /* 62.4us */
165 }
166 write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
167
168 val = read_mmcr_byte(SC520_DRCTMCTL);
169 val &= 0xf0;
170
171 if (cas_precharge_delay==3) {
172 val |= 0x04; /* 3T */
173 } else if (cas_precharge_delay==4) {
174 val |= 0x08; /* 4T */
175 } else if (cas_precharge_delay>4) {
176 val |= 0x0c;
177 }
178
179 if (ras_cas_delay > 3) {
180 val |= 2;
181 } else {
182 val |= 1;
183 }
184 write_mmcr_byte(SC520_DRCTMCTL, val);
185
186
187 /* We read-back the configuration of the dram
188 * controller that the assembly code wrote */
189 dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
190
191
192 bd->bi_dram[0].start = 0;
193 if (dram_ctrl & 0x80) {
194 /* bank 0 enabled */
195 dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
196 bd->bi_dram[0].size = bd->bi_dram[1].start;
197
198 } else {
199 bd->bi_dram[0].size = 0;
200 bd->bi_dram[1].start = bd->bi_dram[0].start;
201 }
202
203 if (dram_ctrl & 0x8000) {
204 /* bank 1 enabled */
205 dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
206 bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start;
207 } else {
208 bd->bi_dram[1].size = 0;
209 bd->bi_dram[2].start = bd->bi_dram[1].start;
210 }
211
212 if (dram_ctrl & 0x800000) {
213 /* bank 2 enabled */
214 dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
215 bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start;
216 } else {
217 bd->bi_dram[2].size = 0;
218 bd->bi_dram[3].start = bd->bi_dram[2].start;
219 }
220
221 if (dram_ctrl & 0x80000000) {
222 /* bank 3 enabled */
223 dram_present = (dram_ctrl & 0x7f000000) >> 2;
224 bd->bi_dram[3].size = dram_present - bd->bi_dram[3].start;
225 } else {
226 bd->bi_dram[3].size = 0;
227 }
228
229
230 #if 0
231 printf("Configured %d bytes of dram\n", dram_present);
232 #endif
233 gd->ram_size = dram_present;
234
235 return dram_present;
236 }
237
238
239 #ifdef CONFIG_PCI
240
241
242 static struct {
243 u8 priority;
244 u16 level_reg;
245 u8 level_bit;
246 } sc520_irq[] = {
247 { SC520_IRQ0, SC520_MPICMODE, 0x01 },
248 { SC520_IRQ1, SC520_MPICMODE, 0x02 },
249 { SC520_IRQ2, SC520_SL1PICMODE, 0x02 },
250 { SC520_IRQ3, SC520_MPICMODE, 0x08 },
251 { SC520_IRQ4, SC520_MPICMODE, 0x10 },
252 { SC520_IRQ5, SC520_MPICMODE, 0x20 },
253 { SC520_IRQ6, SC520_MPICMODE, 0x40 },
254 { SC520_IRQ7, SC520_MPICMODE, 0x80 },
255
256 { SC520_IRQ8, SC520_SL1PICMODE, 0x01 },
257 { SC520_IRQ9, SC520_SL1PICMODE, 0x02 },
258 { SC520_IRQ10, SC520_SL1PICMODE, 0x04 },
259 { SC520_IRQ11, SC520_SL1PICMODE, 0x08 },
260 { SC520_IRQ12, SC520_SL1PICMODE, 0x10 },
261 { SC520_IRQ13, SC520_SL1PICMODE, 0x20 },
262 { SC520_IRQ14, SC520_SL1PICMODE, 0x40 },
263 { SC520_IRQ15, SC520_SL1PICMODE, 0x80 }
264 };
265
266
267 /* The interrupt used for PCI INTA-INTD */
268 int sc520_pci_ints[15] = {
269 -1, -1, -1, -1, -1, -1, -1, -1,
270 -1, -1, -1, -1, -1, -1, -1
271 };
272
273 /* utility function to configure a pci interrupt */
274 int pci_sc520_set_irq(int pci_pin, int irq)
275 {
276 int i;
277
278 # if 0
279 printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
280 #endif
281 if (irq < 0 || irq > 15) {
282 return -1; /* illegal irq */
283 }
284
285 if (pci_pin < 0 || pci_pin > 15) {
286 return -1; /* illegal pci int pin */
287 }
288
289 /* first disable any non-pci interrupt source that use
290 * this level */
291 for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) {
292 if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) {
293 continue;
294 }
295 if (read_mmcr_byte(i) == sc520_irq[irq].priority) {
296 write_mmcr_byte(i, SC520_IRQ_DISABLED);
297 }
298 }
299
300 /* Set the trigger to level */
301 write_mmcr_byte(sc520_irq[irq].level_reg,
302 read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit);
303
304
305 if (pci_pin < 4) {
306 /* PCI INTA-INTD */
307 /* route the interrupt */
308 write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority);
309
310
311 } else {
312 /* GPIRQ0-GPIRQ10 used for additional PCI INTS */
313 write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority);
314
315 /* also set the polarity in this case */
316 write_mmcr_word(SC520_INTPINPOL,
317 read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4)));
318
319 }
320
321 /* register the pin */
322 sc520_pci_ints[pci_pin] = irq;
323
324
325 return 0; /* OK */
326 }
327
328 void pci_sc520_init(struct pci_controller *hose)
329 {
330 hose->first_busno = 0;
331 hose->last_busno = 0xff;
332
333 /* System memory space */
334 pci_set_region(hose->regions + 0,
335 SC520_PCI_MEMORY_BUS,
336 SC520_PCI_MEMORY_PHYS,
337 SC520_PCI_MEMORY_SIZE,
338 PCI_REGION_MEM | PCI_REGION_MEMORY);
339
340 /* PCI memory space */
341 pci_set_region(hose->regions + 1,
342 SC520_PCI_MEM_BUS,
343 SC520_PCI_MEM_PHYS,
344 SC520_PCI_MEM_SIZE,
345 PCI_REGION_MEM);
346
347 /* ISA/PCI memory space */
348 pci_set_region(hose->regions + 2,
349 SC520_ISA_MEM_BUS,
350 SC520_ISA_MEM_PHYS,
351 SC520_ISA_MEM_SIZE,
352 PCI_REGION_MEM);
353
354 /* PCI I/O space */
355 pci_set_region(hose->regions + 3,
356 SC520_PCI_IO_BUS,
357 SC520_PCI_IO_PHYS,
358 SC520_PCI_IO_SIZE,
359 PCI_REGION_IO);
360
361 /* ISA/PCI I/O space */
362 pci_set_region(hose->regions + 4,
363 SC520_ISA_IO_BUS,
364 SC520_ISA_IO_PHYS,
365 SC520_ISA_IO_SIZE,
366 PCI_REGION_IO);
367
368 hose->region_count = 5;
369
370 pci_setup_type1(hose,
371 SC520_REG_ADDR,
372 SC520_REG_DATA);
373
374 pci_register_hose(hose);
375
376 hose->last_busno = pci_hose_scan(hose);
377
378 /* enable target memory acceses on host brige */
379 pci_write_config_word(0, PCI_COMMAND,
380 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
381
382 }
383
384
385 #endif
386
387 #ifdef CFG_TIMER_SC520
388
389
390 void reset_timer(void)
391 {
392 write_mmcr_word(SC520_GPTMR0CNT, 0);
393 write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
394
395 }
396
397 ulong get_timer(ulong base)
398 {
399 /* fixme: 30 or 33 */
400 return read_mmcr_word(SC520_GPTMR0CNT) / 33;
401 }
402
403 void set_timer(ulong t)
404 {
405 /* FixMe: use two cascade coupled timers */
406 write_mmcr_word(SC520_GPTMR0CTL, 0x4001);
407 write_mmcr_word(SC520_GPTMR0CNT, t*33);
408 write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
409 }
410
411
412 void udelay(unsigned long usec)
413 {
414 int m=0;
415 long u;
416
417 read_mmcr_word(SC520_SWTMRMILLI);
418 read_mmcr_word(SC520_SWTMRMICRO);
419
420 #if 0
421 /* do not enable this line, udelay is used in the serial driver -> recursion */
422 printf("udelay: %ld m.u %d.%d tm.tu %d.%d\n", usec, m, u, tm, tu);
423 #endif
424 while (1) {
425
426 m += read_mmcr_word(SC520_SWTMRMILLI);
427 u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000);
428
429 if (usec <= u) {
430 break;
431 }
432 }
433 }
434
435 #endif
436
437 int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
438 {
439 u8 temp=0;
440
441 if (freq >= 8192) {
442 temp |= CTL_CLK_SEL_4;
443 } else if (freq >= 4096) {
444 temp |= CTL_CLK_SEL_8;
445 } else if (freq >= 2048) {
446 temp |= CTL_CLK_SEL_16;
447 } else if (freq >= 1024) {
448 temp |= CTL_CLK_SEL_32;
449 } else if (freq >= 512) {
450 temp |= CTL_CLK_SEL_64;
451 } else if (freq >= 256) {
452 temp |= CTL_CLK_SEL_128;
453 } else if (freq >= 128) {
454 temp |= CTL_CLK_SEL_256;
455 } else {
456 temp |= CTL_CLK_SEL_512;
457 }
458
459 if (!lsb_first) {
460 temp |= MSBF_ENB;
461 }
462
463 if (inv_clock) {
464 temp |= CLK_INV_ENB;
465 }
466
467 if (inv_phase) {
468 temp |= PHS_INV_ENB;
469 }
470
471 write_mmcr_byte(SC520_SSICTL, temp);
472
473 return 0;
474 }
475
476 u8 ssi_txrx_byte(u8 data)
477 {
478 write_mmcr_byte(SC520_SSIXMIT, data);
479 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
480 write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV);
481 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
482 return read_mmcr_byte(SC520_SSIRCV);
483 }
484
485
486 void ssi_tx_byte(u8 data)
487 {
488 write_mmcr_byte(SC520_SSIXMIT, data);
489 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
490 write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT);
491 }
492
493 u8 ssi_rx_byte(void)
494 {
495 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
496 write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV);
497 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
498 return read_mmcr_byte(SC520_SSIRCV);
499 }
500
501 #endif /* CONFIG_SC520 */
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