cpu/ixp/cpu.c

   1 /*
   2  * (C) Copyright 2002
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Marius Groeger <mgroeger@sysgo.de>
   5  *
   6  * (C) Copyright 2002
   7  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   8  * Alex Zuepke <azu@sysgo.de>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /*
  30  * CPU specific code
  31  */
  32
  33 #include <common.h>
  34 #include <command.h>
  35 #include <netdev.h>
  36 #include <asm/arch/ixp425.h>
  37
  38 ulong loops_per_jiffy;
  39
  40 #ifdef CONFIG_USE_IRQ
  41 DECLARE_GLOBAL_DATA_PTR;
  42 #endif
  43
  44 #if defined(CONFIG_DISPLAY_CPUINFO)
  45 int print_cpuinfo (void)
  46 {
  47         unsigned long id;
  48         int speed = 0;
  49
  50         asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id));
  51
  52         puts("CPU:   Intel IXP425 at ");
  53         switch ((id & 0x000003f0) >> 4) {
  54         case 0x1c:
  55                 loops_per_jiffy = 887467;
  56                 speed = 533;
  57                 break;
  58
  59         case 0x1d:
  60                 loops_per_jiffy = 666016;
  61                 speed = 400;
  62                 break;
  63
  64         case 0x1f:
  65                 loops_per_jiffy = 442901;
  66                 speed = 266;
  67                 break;
  68         }
  69
  70         if (speed)
  71                 printf("%d MHz\n", speed);
  72         else
  73                 puts("unknown revision\n");
  74
  75         return 0;
  76 }
  77 #endif /* CONFIG_DISPLAY_CPUINFO */
  78
  79 int cpu_init (void)
  80 {
  81         /*
  82          * setup up stacks if necessary
  83          */
  84 #ifdef CONFIG_USE_IRQ
  85         IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
  86         FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
  87 #endif
  88
  89 #if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI)
  90         pci_init();
  91 #endif
  92         return 0;
  93 }
  94
  95 int cleanup_before_linux (void)
  96 {
  97         /*
  98          * this function is called just before we call linux
  99          * it prepares the processor for linux
 100          *
 101          * just disable everything that can disturb booting linux
 102          */
 103
 104         unsigned long i;
 105
 106         disable_interrupts ();
 107
 108         /* turn off I-cache */
 109         asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 110         i &= ~0x1000;
 111         asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 112
 113         /* flush I-cache */
 114         asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
 115
 116         return (0);
 117 }
 118
 119 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 120 {
 121         printf ("resetting ...\n");
 122
 123         udelay (50000);                         /* wait 50 ms */
 124         disable_interrupts ();
 125         reset_cpu (0);
 126
 127         /*NOTREACHED*/
 128         return (0);
 129 }
 130
 131 /* taken from blob */
 132 void icache_enable (void)
 133 {
 134         register u32 i;
 135
 136         /* read control register */
 137         asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 138
 139         /* set i-cache */
 140         i |= 0x1000;
 141
 142         /* write back to control register */
 143         asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 144 }
 145
 146 void icache_disable (void)
 147 {
 148         register u32 i;
 149
 150         /* read control register */
 151         asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 152
 153         /* clear i-cache */
 154         i &= ~0x1000;
 155
 156         /* write back to control register */
 157         asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 158
 159         /* flush i-cache */
 160         asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
 161 }
 162
 163 int icache_status (void)
 164 {
 165         register u32 i;
 166
 167         /* read control register */
 168         asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 169
 170         /* return bit */
 171         return (i & 0x1000);
 172 }
 173
 174 /* we will never enable dcache, because we have to setup MMU first */
 175 void dcache_enable (void)
 176 {
 177         return;
 178 }
 179
 180 void dcache_disable (void)
 181 {
 182         return;
 183 }
 184
 185 int dcache_status (void)
 186 {
 187         return 0;                                       /* always off */
 188 }
 189
 190 /* FIXME */
 191 /*
 192 void pci_init(void)
 193 {
 194         return;
 195 }
 196 */
 197
 198 #ifdef CONFIG_BOOTCOUNT_LIMIT
 199
 200 void bootcount_store (ulong a)
 201 {
 202         volatile ulong *save_addr = (volatile ulong *)(CONFIG_SYS_BOOTCOUNT_ADDR);
 203
 204         save_addr[0] = a;
 205         save_addr[1] = BOOTCOUNT_MAGIC;
 206 }
 207
 208 ulong bootcount_load (void)
 209 {
 210         volatile ulong *save_addr = (volatile ulong *)(CONFIG_SYS_BOOTCOUNT_ADDR);
 211
 212         if (save_addr[1] != BOOTCOUNT_MAGIC)
 213                 return 0;
 214         else
 215                 return save_addr[0];
 216 }
 217
 218 #endif /* CONFIG_BOOTCOUNT_LIMIT */
 219
 220 int cpu_eth_init(bd_t *bis)
 221 {
 222 #ifdef CONFIG_IXP4XX_NPE
 223         npe_initialize(bis);
 224 #endif
 225         return 0;
 226 }