cpu/ixp/npe/include/IxEthMii_p.h

   1 /**
   2  * @file IxEthMii_p.h
   3  *
   4  * @author Intel Corporation
   5  * @date
   6  *
   7  * @brief  MII Header file
   8  *
   9  * Design Notes:
  10  *
  11  *
  12  * @par
  13  * IXP400 SW Release version 2.0
  14  *
  15  * -- Copyright Notice --
  16  *
  17  * @par
  18  * Copyright 2001-2005, Intel Corporation.
  19  * All rights reserved.
  20  *
  21  * @par
  22  * Redistribution and use in source and binary forms, with or without
  23  * modification, are permitted provided that the following conditions
  24  * are met:
  25  * 1. Redistributions of source code must retain the above copyright
  26  *    notice, this list of conditions and the following disclaimer.
  27  * 2. Redistributions in binary form must reproduce the above copyright
  28  *    notice, this list of conditions and the following disclaimer in the
  29  *    documentation and/or other materials provided with the distribution.
  30  * 3. Neither the name of the Intel Corporation nor the names of its contributors
  31  *    may be used to endorse or promote products derived from this software
  32  *    without specific prior written permission.
  33  *
  34  * @par
  35  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
  36  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  37  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  38  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
  39  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  40  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  41  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  42  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  43  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  44  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  45  * SUCH DAMAGE.
  46  *
  47  * @par
  48  * -- End of Copyright Notice --
  49  */
  50
  51 #ifndef IxEthMii_p_H
  52 #define IxEthMii_p_H
  53
  54
  55 /* MII definitions - these have been verified against the LXT971 and
  56  LXT972 PHYs*/
  57
  58 #define IX_ETH_MII_MAX_REG_NUM  0x20  /* max number of registers */
  59
  60 #define IX_ETH_MII_CTRL_REG     0x0     /* Control Register */
  61 #define IX_ETH_MII_STAT_REG     0x1     /* Status Register */
  62 #define IX_ETH_MII_PHY_ID1_REG  0x2     /* PHY identifier 1 Register */
  63 #define IX_ETH_MII_PHY_ID2_REG  0x3     /* PHY identifier 2 Register */
  64 #define IX_ETH_MII_AN_ADS_REG   0x4     /* Auto-Negotiation       */
  65                                         /* Advertisement Register */
  66 #define IX_ETH_MII_AN_PRTN_REG  0x5     /* Auto-Negotiation         */
  67                                         /* partner ability Register */
  68 #define IX_ETH_MII_AN_EXP_REG   0x6     /* Auto-Negotiation   */
  69                                         /* Expansion Register */
  70 #define IX_ETH_MII_AN_NEXT_REG  0x7     /* Auto-Negotiation            */
  71                                         /* next-page transmit Register */
  72
  73 #define IX_ETH_MII_STAT2_REG    0x11    /* Status Register 2*/
  74
  75
  76 /* MII control register bit  */
  77
  78 #define IX_ETH_MII_CR_COLL_TEST  0x0080  /* collision test */
  79 #define IX_ETH_MII_CR_FDX        0x0100  /* FDX =1, half duplex =0 */
  80 #define IX_ETH_MII_CR_RESTART    0x0200  /* restart auto negotiation */
  81 #define IX_ETH_MII_CR_ISOLATE    0x0400  /* isolate PHY from MII */
  82 #define IX_ETH_MII_CR_POWER_DOWN 0x0800  /* power down */
  83 #define IX_ETH_MII_CR_AUTO_EN    0x1000  /* auto-negotiation enable */
  84 #define IX_ETH_MII_CR_100        0x2000  /* 0 = 10mb, 1 = 100mb */
  85 #define IX_ETH_MII_CR_LOOPBACK   0x4000  /* 0 = normal, 1 = loopback */
  86 #define IX_ETH_MII_CR_RESET      0x8000  /* 0 = normal, 1 = PHY reset */
  87 #define IX_ETH_MII_CR_NORM_EN    0x0000  /* just enable the PHY */
  88 #define IX_ETH_MII_CR_DEF_0_MASK 0xca7f  /* they must return zero */
  89 #define IX_ETH_MII_CR_RES_MASK   0x007f  /* reserved bits, return zero */
  90
  91 /* MII Status register bit definitions */
  92
  93 #define IX_ETH_MII_SR_LINK_STATUS   0x0004 /* link Status -- 1 = link */
  94 #define IX_ETH_MII_SR_AUTO_SEL      0x0008 /* auto speed select capable */
  95 #define IX_ETH_MII_SR_REMOTE_FAULT  0x0010 /* Remote fault detect */
  96 #define IX_ETH_MII_SR_AUTO_NEG      0x0020 /* auto negotiation complete */
  97 #define IX_ETH_MII_SR_10T_HALF_DPX  0x0800 /* 10BaseT HD capable */
  98 #define IX_ETH_MII_SR_10T_FULL_DPX  0x1000 /* 10BaseT FD capable */
  99 #define IX_ETH_MII_SR_TX_HALF_DPX   0x2000 /* TX HD capable */
 100 #define IX_ETH_MII_SR_TX_FULL_DPX   0x4000 /* TX FD capable */
 101 #define IX_ETH_MII_SR_T4            0x8000 /* T4 capable */
 102 #define IX_ETH_MII_SR_ABIL_MASK     0xff80 /* abilities mask */
 103 #define IX_ETH_MII_SR_EXT_CAP       0x0001 /* extended capabilities */
 104
 105
 106 /* LXT971/2 Status 2 register bit definitions */
 107 #define IX_ETH_MII_SR2_100          0x4000
 108 #define IX_ETH_MII_SR2_TX           0x2000
 109 #define IX_ETH_MII_SR2_RX           0x1000
 110 #define IX_ETH_MII_SR2_COL          0x0800
 111 #define IX_ETH_MII_SR2_LINK         0x0400
 112 #define IX_ETH_MII_SR2_FD           0x0200
 113 #define IX_ETH_MII_SR2_AUTO         0x0100
 114 #define IX_ETH_MII_SR2_AUTO_CMPLT   0x0080
 115 #define IX_ETH_MII_SR2_POLARITY     0x0020
 116 #define IX_ETH_MII_SR2_PAUSE        0x0010
 117 #define IX_ETH_MII_SR2_ERROR        0x0008
 118
 119 /* MII Link Code word  bit definitions */
 120
 121 #define IX_ETH_MII_BP_FAULT     0x2000          /* remote fault */
 122 #define IX_ETH_MII_BP_ACK       0x4000          /* acknowledge */
 123 #define IX_ETH_MII_BP_NP        0x8000          /* nexp page is supported */
 124
 125 /* MII Next Page bit definitions */
 126
 127 #define IX_ETH_MII_NP_TOGGLE 0x0800             /* toggle bit */
 128 #define IX_ETH_MII_NP_ACK2       0x1000         /* acknowledge two */
 129 #define IX_ETH_MII_NP_MSG        0x2000         /* message page */
 130 #define IX_ETH_MII_NP_ACK1       0x4000         /* acknowledge one */
 131 #define IX_ETH_MII_NP_NP         0x8000         /* nexp page will follow */
 132
 133 /* MII Expansion Register bit definitions */
 134
 135 #define IX_ETH_MII_EXP_FAULT    0x0010  /* parallel detection fault */
 136 #define IX_ETH_MII_EXP_PRTN_NP  0x0008  /* link partner next-page able */
 137 #define IX_ETH_MII_EXP_LOC_NP   0x0004  /* local PHY next-page able */
 138 #define IX_ETH_MII_EXP_PR           0x0002  /* full page received */
 139 #define IX_ETH_MII_EXP_PRT_AN   0x0001  /* link partner auto neg able */
 140
 141 /* technology ability field bit definitions */
 142
 143 #define IX_ETH_MII_TECH_10BASE_T          0x0020  /* 10Base-T */
 144 #define IX_ETH_MII_TECH_10BASE_FD         0x0040  /* 10Base-T Full Duplex */
 145 #define IX_ETH_MII_TECH_100BASE_TX        0x0080  /* 100Base-TX */
 146 #define IX_ETH_MII_TECH_100BASE_TX_FD 0x0100  /* 100Base-TX Full Duplex */
 147
 148 #define IX_ETH_MII_TECH_100BASE_T4      0x0200  /* 100Base-T4 */
 149 #define IX_ETH_MII_ADS_TECH_MASK        0x1fe0  /* technology abilities mask */
 150 #define IX_ETH_MII_TECH_MASK    IX_ETH_MII_ADS_TECH_MASK
 151 #define IX_ETH_MII_ADS_SEL_MASK 0x001f  /* selector field mask */
 152
 153 #define IX_ETH_MII_AN_FAIL     0x10    /* auto-negotiation fail */
 154 #define IX_ETH_MII_STAT_FAIL   0x20    /* errors in the status register */
 155 #define IX_ETH_MII_PHY_NO_ABLE 0x40    /* the PHY lacks some abilities */
 156
 157 /* Definitions for MII access routines*/
 158
 159 #define IX_ETH_MII_GO                  BIT(31)
 160 #define IX_ETH_MII_WRITE               BIT(26)
 161 #define IX_ETH_MII_TIMEOUT_10TH_SECS       (5)
 162 #define IX_ETH_MII_10TH_SEC_IN_MILLIS    (100)
 163 #define IX_ETH_MII_READ_FAIL           BIT(31)
 164
 165 /* When we reset the PHY we delay for 2 seconds to allow the reset to
 166    complete*/
 167 #define IX_ETH_MII_RESET_DELAY_MS  (2000)
 168 #define IX_ETH_MII_RESET_POLL_MS     (50)
 169
 170 #define IX_ETH_MII_REG_SHL    16
 171 #define IX_ETH_MII_ADDR_SHL   21
 172
 173 /* supported PHYs */
 174 #define IX_ETH_MII_LXT971_PHY_ID        0x001378E0
 175 #define IX_ETH_MII_LXT972_PHY_ID        0x001378E2
 176 #define IX_ETH_MII_LXT973_PHY_ID        0x00137A10
 177 #define IX_ETH_MII_LXT973A3_PHY_ID      0x00137A11
 178 #define IX_ETH_MII_KS8995_PHY_ID        0x00221450
 179 #define IX_ETH_MII_LXT9785_PHY_ID       0x001378FF
 180
 181
 182 #define IX_ETH_MII_INVALID_PHY_ID 0x00000000
 183 #define IX_ETH_MII_UNKNOWN_PHY_ID 0xffffffff
 184
 185 #endif  /*IxEthAccMii_p_H*/