cpu/mc9328/interrupts.c

   1 /*
   2  * (C) Copyright 2002
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Marius Groeger <mgroeger@sysgo.de>
   5  *
   6  * (C) Copyright 2002
   7  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   8  * Alex Zuepke <azu@sysgo.de>
   9  *
  10  * (C) Copyright 2002
  11  * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 #include <common.h>
  33 #include <arm920t.h>
  34 #include <mc9328.h>
  35
  36 #include <asm/proc-armv/ptrace.h>
  37
  38 extern void reset_cpu(ulong addr);
  39 int timer_load_val = 0;
  40
  41 #ifdef CONFIG_USE_IRQ
  42 /* enable IRQ interrupts */
  43 void enable_interrupts (void)
  44 {
  45         unsigned long temp;
  46         __asm__ __volatile__("mrs %0, cpsr\n"
  47                              "bic %0, %0, #0x80\n"
  48                              "msr cpsr_c, %0"
  49                              : "=r" (temp)
  50                              :
  51                              : "memory");
  52 }
  53
  54
  55 /*
  56  * disable IRQ/FIQ interrupts
  57  * returns true if interrupts had been enabled before we disabled them
  58  */
  59 int disable_interrupts (void)
  60 {
  61         unsigned long old,temp;
  62         __asm__ __volatile__("mrs %0, cpsr\n"
  63                              "orr %1, %0, #0xc0\n"
  64                              "msr cpsr_c, %1"
  65                              : "=r" (old), "=r" (temp)
  66                              :
  67                              : "memory");
  68         return (old & 0x80) == 0;
  69 }
  70 #else
  71 void enable_interrupts (void)
  72 {
  73         return;
  74 }
  75 int disable_interrupts (void)
  76 {
  77         return 0;
  78 }
  79 #endif
  80
  81
  82 void bad_mode (void)
  83 {
  84         panic ("Resetting CPU ...\n");
  85         reset_cpu (0);
  86 }
  87
  88 void show_regs (struct pt_regs *regs)
  89 {
  90         unsigned long flags;
  91         const char *processor_modes[] = {
  92         "USER_26",      "FIQ_26",       "IRQ_26",       "SVC_26",
  93         "UK4_26",       "UK5_26",       "UK6_26",       "UK7_26",
  94         "UK8_26",       "UK9_26",       "UK10_26",      "UK11_26",
  95         "UK12_26",      "UK13_26",      "UK14_26",      "UK15_26",
  96         "USER_32",      "FIQ_32",       "IRQ_32",       "SVC_32",
  97         "UK4_32",       "UK5_32",       "UK6_32",       "ABT_32",
  98         "UK8_32",       "UK9_32",       "UK10_32",      "UND_32",
  99         "UK12_32",      "UK13_32",      "UK14_32",      "SYS_32",
 100         };
 101
 102         flags = condition_codes (regs);
 103
 104         printf ("pc : [<%08lx>]    lr : [<%08lx>]\n"
 105                 "sp : %08lx  ip : %08lx  fp : %08lx\n",
 106                 instruction_pointer (regs),
 107                 regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
 108         printf ("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
 109                 regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
 110         printf ("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
 111                 regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
 112         printf ("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
 113                 regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
 114         printf ("Flags: %c%c%c%c",
 115                 flags & CC_N_BIT ? 'N' : 'n',
 116                 flags & CC_Z_BIT ? 'Z' : 'z',
 117                 flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
 118         printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
 119                 interrupts_enabled (regs) ? "on" : "off",
 120                 fast_interrupts_enabled (regs) ? "on" : "off",
 121                 processor_modes[processor_mode (regs)],
 122                 thumb_mode (regs) ? " (T)" : "");
 123 }
 124
 125 void do_undefined_instruction (struct pt_regs *pt_regs)
 126 {
 127         printf ("undefined instruction\n");
 128         show_regs (pt_regs);
 129         bad_mode ();
 130 }
 131
 132 void do_software_interrupt (struct pt_regs *pt_regs)
 133 {
 134         printf ("software interrupt\n");
 135         show_regs (pt_regs);
 136         bad_mode ();
 137 }
 138
 139 void do_prefetch_abort (struct pt_regs *pt_regs)
 140 {
 141         printf ("prefetch abort\n");
 142         show_regs (pt_regs);
 143         bad_mode ();
 144 }
 145
 146 void do_data_abort (struct pt_regs *pt_regs)
 147 {
 148         printf ("data abort\n");
 149         show_regs (pt_regs);
 150         bad_mode ();
 151 }
 152
 153 void do_not_used (struct pt_regs *pt_regs)
 154 {
 155         printf ("not used\n");
 156         show_regs (pt_regs);
 157         bad_mode ();
 158 }
 159
 160 void do_fiq (struct pt_regs *pt_regs)
 161 {
 162         printf ("fast interrupt request\n");
 163         show_regs (pt_regs);
 164         bad_mode ();
 165 }
 166
 167 void do_irq (struct pt_regs *pt_regs)
 168 {
 169         printf ("interrupt request\n");
 170         show_regs (pt_regs);
 171         bad_mode ();
 172 }
 173
 174
 175 int interrupt_init (void)
 176 {
 177
 178 /* we don't use interrupt */
 179         return(0);
 180 }
 181
 182 /*
 183  * timer without interrupts
 184  */
 185
 186 void reset_timer (void)
 187 {
 188         reset_timer_masked ();
 189 }
 190
 191 ulong get_timer (ulong base)
 192 {
 193         return get_timer_masked ();
 194 }
 195
 196 void set_timer (ulong t)
 197 {
 198 /* Nop  */
 199 }
 200
 201 void udelay (unsigned long usec)
 202 {
 203         udelay_masked (usec);
 204 }
 205
 206 void reset_timer_masked (void)
 207 {
 208         u32     tmp;
 209         MX1_TCTL1       = 0x09;
 210         tmp = 0x1f;             /* a little delay for timer to reset */
 211         MX1_TPRER1      = 0x1f;
 212         MX1_TCTL1       = 0x19;
 213 }
 214
 215 ulong get_timer_masked (void)
 216 {
 217         return MX1_TCN1;
 218 }
 219
 220 void udelay_masked (unsigned long usec)
 221 {
 222         ulong tmo;
 223
 224         tmo = usec / 1000;
 225         tmo *= CFG_HZ;
 226         tmo /= 1000;
 227
 228         reset_timer_masked ();
 229
 230         while (get_timer_masked () < tmo);
 231 }
 232
 233 /*
 234  * This function is derived from PowerPC code (read timebase as long long).
 235  * On ARM it just returns the timer value.
 236  */
 237 unsigned long long get_ticks(void)
 238 {
 239         return get_timer(0);
 240 }
 241
 242 /*
 243  * This function is derived from PowerPC code (timebase clock frequency).
 244  * On ARM it returns the number of timer ticks per second.
 245  */
 246
 247 ulong  get_tbclk (void) {
 248         return CFG_HZ;
 249 }
 250