cpu/mcf52x2/cpu_init.c

   1 /*
   2  * (C) Copyright 2003
   3  * Josef Baumgartner <josef.baumgartner@telex.de>
   4  *
   5  * MCF5282 additionals
   6  * (C) Copyright 2005
   7  * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
   8  * (c) Copyright 2010
   9  * Arcturus Networks Inc. <www.arcturusnetworks.com>
  10  *
  11  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  12  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  13  * Hayden Fraser (Hayden.Fraser@freescale.com)
  14  *
  15  * MCF5275 additions
  16  * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
  17  *
  18  * See file CREDITS for list of people who contributed to this
  19  * project.
  20  *
  21  * This program is free software; you can redistribute it and/or
  22  * modify it under the terms of the GNU General Public License as
  23  * published by the Free Software Foundation; either version 2 of
  24  * the License, or (at your option) any later version.
  25  *
  26  * This program is distributed in the hope that it will be useful,
  27  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  28  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  29  * GNU General Public License for more details.
  30  *
  31  * You should have received a copy of the GNU General Public License
  32  * along with this program; if not, write to the Free Software
  33  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  34  * MA 02111-1307 USA
  35  */
  36
  37 #include <common.h>
  38 #include <watchdog.h>
  39 #include <asm/immap.h>
  40
  41 #if defined(CONFIG_CMD_NET)
  42 #include <config.h>
  43 #include <net.h>
  44 #include <asm/fec.h>
  45 #endif
  46
  47 #ifndef CONFIG_M5272
  48 /* Only 5272 Flexbus chipselect is different from the rest */
  49 void init_fbcs(void)
  50 {
  51         volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
  52
  53 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
  54      && defined(CONFIG_SYS_CS0_CTRL))
  55         fbcs->csar0 = CONFIG_SYS_CS0_BASE;
  56         fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
  57         fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
  58 #else
  59 #warning "Chip Select 0 are not initialized/used"
  60 #endif
  61 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
  62      && defined(CONFIG_SYS_CS1_CTRL))
  63         fbcs->csar1 = CONFIG_SYS_CS1_BASE;
  64         fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
  65         fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
  66 #endif
  67 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
  68      && defined(CONFIG_SYS_CS2_CTRL))
  69         fbcs->csar2 = CONFIG_SYS_CS2_BASE;
  70         fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
  71         fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
  72 #endif
  73 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
  74      && defined(CONFIG_SYS_CS3_CTRL))
  75         fbcs->csar3 = CONFIG_SYS_CS3_BASE;
  76         fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
  77         fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
  78 #endif
  79 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
  80      && defined(CONFIG_SYS_CS4_CTRL))
  81         fbcs->csar4 = CONFIG_SYS_CS4_BASE;
  82         fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
  83         fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
  84 #endif
  85 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
  86      && defined(CONFIG_SYS_CS5_CTRL))
  87         fbcs->csar5 = CONFIG_SYS_CS5_BASE;
  88         fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
  89         fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
  90 #endif
  91 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
  92      && defined(CONFIG_SYS_CS6_CTRL))
  93         fbcs->csar6 = CONFIG_SYS_CS6_BASE;
  94         fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
  95         fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
  96 #endif
  97 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
  98      && defined(CONFIG_SYS_CS7_CTRL))
  99         fbcs->csar7 = CONFIG_SYS_CS7_BASE;
 100         fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
 101         fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
 102 #endif
 103 }
 104 #endif
 105
 106 #if defined(CONFIG_M5208)
 107 void cpu_init_f(void)
 108 {
 109         volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
 110
 111 #ifndef CONFIG_WATCHDOG
 112         volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
 113
 114         /* Disable the watchdog if we aren't using it */
 115         wdg->cr = 0;
 116 #endif
 117
 118         scm1->mpr = 0x77777777;
 119         scm1->pacra = 0;
 120         scm1->pacrb = 0;
 121         scm1->pacrc = 0;
 122         scm1->pacrd = 0;
 123         scm1->pacre = 0;
 124         scm1->pacrf = 0;
 125
 126         /* FlexBus Chipselect */
 127         init_fbcs();
 128
 129         icache_enable();
 130 }
 131
 132 /* initialize higher level parts of CPU like timers */
 133 int cpu_init_r(void)
 134 {
 135         return (0);
 136 }
 137
 138 void uart_port_conf(void)
 139 {
 140         volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 141
 142         /* Setup Ports: */
 143         switch (CONFIG_SYS_UART_PORT) {
 144         case 0:
 145                 gpio->par_uart &= GPIO_PAR_UART0_MASK;
 146                 gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
 147                 break;
 148         case 1:
 149                 gpio->par_uart &= GPIO_PAR_UART0_MASK;
 150                 gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
 151                 break;
 152         case 2:
 153 #ifdef CONFIG_SYS_UART2_PRI_GPIO
 154                 gpio->par_timer &=
 155                     (GPIO_PAR_TMR_TIN0_MASK | GPIO_PAR_TMR_TIN1_MASK);
 156                 gpio->par_timer |=
 157                     (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
 158 #endif
 159 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
 160                 gpio->par_feci2c &=
 161                     (GPIO_PAR_FECI2C_MDC_MASK | GPIO_PAR_FECI2C_MDIO_MASK);
 162                 gpio->par_feci2c |=
 163                     (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
 164 #endif
 165 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
 166                 gpio->par_feci2c &=
 167                     (GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
 168                 gpio->par_feci2c |=
 169                     (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
 170 #endif
 171                 break;
 172         }
 173 }
 174
 175 #if defined(CONFIG_CMD_NET)
 176 int fecpin_setclear(struct eth_device *dev, int setclear)
 177 {
 178         volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 179
 180         if (setclear) {
 181                 gpio->par_fec |=
 182                     GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
 183                 gpio->par_feci2c |=
 184                     GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
 185         } else {
 186                 gpio->par_fec &=
 187                     (GPIO_PAR_FEC_7W_MASK & GPIO_PAR_FEC_MII_MASK);
 188                 gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_MASK;
 189         }
 190         return 0;
 191 }
 192 #endif                          /* CONFIG_CMD_NET */
 193 #endif                          /* CONFIG_M5208 */
 194
 195 #if defined(CONFIG_M5253)
 196 /*
 197  * Breath some life into the CPU...
 198  *
 199  * Set up the memory map,
 200  * initialize a bunch of registers,
 201  * initialize the UPM's
 202  */
 203 void cpu_init_f(void)
 204 {
 205         mbar_writeByte(MCFSIM_MPARK, 0x40);     /* 5249 Internal Core takes priority over DMA */
 206         mbar_writeByte(MCFSIM_SYPCR, 0x00);
 207         mbar_writeByte(MCFSIM_SWIVR, 0x0f);
 208         mbar_writeByte(MCFSIM_SWSR, 0x00);
 209         mbar_writeByte(MCFSIM_SWDICR, 0x00);
 210         mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
 211         mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
 212         mbar_writeByte(MCFSIM_I2CICR, 0x00);
 213         mbar_writeByte(MCFSIM_UART1ICR, 0x00);
 214         mbar_writeByte(MCFSIM_UART2ICR, 0x00);
 215         mbar_writeByte(MCFSIM_ICR6, 0x00);
 216         mbar_writeByte(MCFSIM_ICR7, 0x00);
 217         mbar_writeByte(MCFSIM_ICR8, 0x00);
 218         mbar_writeByte(MCFSIM_ICR9, 0x00);
 219         mbar_writeByte(MCFSIM_QSPIICR, 0x00);
 220
 221         mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
 222         mbar2_writeByte(MCFSIM_INTBASE, 0x40);  /* Base interrupts at 64 */
 223         mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
 224
 225         /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
 226
 227         /* FlexBus Chipselect */
 228         init_fbcs();
 229
 230 #ifdef CONFIG_FSL_I2C
 231         CONFIG_SYS_I2C_PINMUX_REG =
 232             CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
 233         CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
 234 #ifdef CONFIG_SYS_I2C2_OFFSET
 235         CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
 236         CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
 237 #endif
 238 #endif
 239
 240         /* enable instruction cache now */
 241         icache_enable();
 242 }
 243
 244 /*initialize higher level parts of CPU like timers */
 245 int cpu_init_r(void)
 246 {
 247         return (0);
 248 }
 249
 250 void uart_port_conf(void)
 251 {
 252         /* Setup Ports: */
 253         switch (CONFIG_SYS_UART_PORT) {
 254         case 0:
 255                 break;
 256         case 1:
 257                 break;
 258         case 2:
 259                 break;
 260         }
 261 }
 262 #endif                          /* #if defined(CONFIG_M5253) */
 263
 264 #if defined(CONFIG_M5271)
 265 void cpu_init_f(void)
 266 {
 267 #ifndef CONFIG_WATCHDOG
 268         /* Disable the watchdog if we aren't using it */
 269         mbar_writeShort(MCF_WTM_WCR, 0);
 270 #endif
 271
 272         /* FlexBus Chipselect */
 273         init_fbcs();
 274
 275 #ifdef CONFIG_SYS_MCF_SYNCR
 276         /* Set clockspeed according to board header file */
 277         mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
 278 #else
 279         /* Set clockspeed to 100MHz */
 280         mbar_writeLong(MCF_FMPLL_SYNCR,
 281                         MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
 282 #endif
 283         while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
 284 }
 285
 286 /*
 287  * initialize higher level parts of CPU like timers
 288  */
 289 int cpu_init_r(void)
 290 {
 291         return (0);
 292 }
 293
 294 void uart_port_conf(void)
 295 {
 296         /* Setup Ports: */
 297         switch (CONFIG_SYS_UART_PORT) {
 298         case 0:
 299                 mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
 300                                 MCF_GPIO_PAR_UART_U0RXD);
 301                 break;
 302         case 1:
 303                 mbar_writeShort(MCF_GPIO_PAR_UART,
 304                                 MCF_GPIO_PAR_UART_U1RXD_UART1 |
 305                                 MCF_GPIO_PAR_UART_U1TXD_UART1);
 306                 break;
 307         case 2:
 308                 mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
 309                 break;
 310         }
 311 }
 312
 313 #if defined(CONFIG_CMD_NET)
 314 int fecpin_setclear(struct eth_device *dev, int setclear)
 315 {
 316         if (setclear) {
 317                 /* Enable Ethernet pins */
 318                 mbar_writeByte(MCF_GPIO_PAR_FECI2C,
 319                                (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
 320         } else {
 321         }
 322
 323         return 0;
 324 }
 325 #endif                          /* CONFIG_CMD_NET */
 326 #endif
 327
 328 #if defined(CONFIG_M5272)
 329 /*
 330  * Breath some life into the CPU...
 331  *
 332  * Set up the memory map,
 333  * initialize a bunch of registers,
 334  * initialize the UPM's
 335  */
 336 void cpu_init_f(void)
 337 {
 338         /* if we come from RAM we assume the CPU is
 339          * already initialized.
 340          */
 341 #ifndef CONFIG_MONITOR_IS_IN_RAM
 342         volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
 343         volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
 344         volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
 345
 346         sysctrl->sc_scr = CONFIG_SYS_SCR;
 347         sysctrl->sc_spr = CONFIG_SYS_SPR;
 348
 349         /* Setup Ports: */
 350         gpio->gpio_pacnt = CONFIG_SYS_PACNT;
 351         gpio->gpio_paddr = CONFIG_SYS_PADDR;
 352         gpio->gpio_padat = CONFIG_SYS_PADAT;
 353         gpio->gpio_pbcnt = CONFIG_SYS_PBCNT;
 354         gpio->gpio_pbddr = CONFIG_SYS_PBDDR;
 355         gpio->gpio_pbdat = CONFIG_SYS_PBDAT;
 356         gpio->gpio_pdcnt = CONFIG_SYS_PDCNT;
 357
 358         /* Memory Controller: */
 359         csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM;
 360         csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM;
 361
 362 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
 363         csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM;
 364         csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM;
 365 #endif
 366
 367 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 368         csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM;
 369         csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM;
 370 #endif
 371
 372 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
 373         csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM;
 374         csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM;
 375 #endif
 376
 377 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
 378         csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM;
 379         csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM;
 380 #endif
 381
 382 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
 383         csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM;
 384         csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM;
 385 #endif
 386
 387 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
 388         csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM;
 389         csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM;
 390 #endif
 391
 392 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
 393         csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM;
 394         csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM;
 395 #endif
 396
 397 #endif                          /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
 398
 399         /* enable instruction cache now */
 400         icache_enable();
 401
 402 }
 403
 404 /*
 405  * initialize higher level parts of CPU like timers
 406  */
 407 int cpu_init_r(void)
 408 {
 409         return (0);
 410 }
 411
 412 void uart_port_conf(void)
 413 {
 414         volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 415
 416         /* Setup Ports: */
 417         switch (CONFIG_SYS_UART_PORT) {
 418         case 0:
 419                 gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
 420                 gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
 421                 break;
 422         case 1:
 423                 gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
 424                 gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
 425                 break;
 426         }
 427 }
 428
 429 #if defined(CONFIG_CMD_NET)
 430 int fecpin_setclear(struct eth_device *dev, int setclear)
 431 {
 432         volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 433
 434         if (setclear) {
 435                 gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
 436                                     GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
 437                                     GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
 438                                     GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
 439         } else {
 440         }
 441         return 0;
 442 }
 443 #endif                          /* CONFIG_CMD_NET */
 444 #endif                          /* #if defined(CONFIG_M5272) */
 445
 446 #if defined(CONFIG_M5275)
 447
 448 /*
 449  * Breathe some life into the CPU...
 450  *
 451  * Set up the memory map,
 452  * initialize a bunch of registers,
 453  * initialize the UPM's
 454  */
 455 void cpu_init_f(void)
 456 {
 457         /*
 458          * if we come from RAM we assume the CPU is
 459          * already initialized.
 460          */
 461
 462 #ifndef CONFIG_MONITOR_IS_IN_RAM
 463         volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
 464         volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
 465
 466         /* Kill watchdog so we can initialize the PLL */
 467         wdog_reg->wcr = 0;
 468
 469         /* FlexBus Chipselect */
 470         init_fbcs();
 471 #endif                          /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
 472
 473 #ifdef CONFIG_FSL_I2C
 474         CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
 475         CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
 476 #endif
 477
 478         /* enable instruction cache now */
 479         icache_enable();
 480 }
 481
 482 /*
 483  * initialize higher level parts of CPU like timers
 484  */
 485 int cpu_init_r(void)
 486 {
 487         return (0);
 488 }
 489
 490 void uart_port_conf(void)
 491 {
 492         volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 493
 494         /* Setup Ports: */
 495         switch (CONFIG_SYS_UART_PORT) {
 496         case 0:
 497                 gpio->par_uart |= UART0_ENABLE_MASK;
 498                 break;
 499         case 1:
 500                 gpio->par_uart |= UART1_ENABLE_MASK;
 501                 break;
 502         case 2:
 503                 gpio->par_uart |= UART2_ENABLE_MASK;
 504                 break;
 505         }
 506 }
 507
 508 #if defined(CONFIG_CMD_NET)
 509 int fecpin_setclear(struct eth_device *dev, int setclear)
 510 {
 511         struct fec_info_s *info = (struct fec_info_s *) dev->priv;
 512         volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
 513
 514         if (setclear) {
 515                 /* Enable Ethernet pins */
 516                 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
 517                         gpio->par_feci2c |= 0x0F00;
 518                         gpio->par_fec0hl |= 0xC0;
 519                 } else {
 520                         gpio->par_feci2c |= 0x00A0;
 521                         gpio->par_fec1hl |= 0xC0;
 522                 }
 523         } else {
 524                 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
 525                         gpio->par_feci2c &= ~0x0F00;
 526                         gpio->par_fec0hl &= ~0xC0;
 527                 } else {
 528                         gpio->par_feci2c &= ~0x00A0;
 529                         gpio->par_fec1hl &= ~0xC0;
 530                 }
 531         }
 532
 533         return 0;
 534 }
 535 #endif                          /* CONFIG_CMD_NET */
 536 #endif                          /* #if defined(CONFIG_M5275) */
 537
 538 #if defined(CONFIG_M5282)
 539 /*
 540  * Breath some life into the CPU...
 541  *
 542  * Set up the memory map,
 543  * initialize a bunch of registers,
 544  * initialize the UPM's
 545  */
 546 void cpu_init_f(void)
 547 {
 548 #ifndef CONFIG_WATCHDOG
 549         /* disable watchdog if we aren't using it */
 550         MCFWTM_WCR = 0;
 551 #endif
 552
 553 #ifndef CONFIG_MONITOR_IS_IN_RAM
 554         /* Set speed /PLL */
 555         MCFCLOCK_SYNCR =
 556             MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
 557             MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
 558         while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
 559
 560         MCFGPIO_PBCDPAR = 0xc0;
 561
 562         /* Set up the GPIO ports */
 563 #ifdef CONFIG_SYS_PEPAR
 564         MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
 565 #endif
 566 #ifdef  CONFIG_SYS_PFPAR
 567         MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
 568 #endif
 569 #ifdef CONFIG_SYS_PJPAR
 570         MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
 571 #endif
 572 #ifdef CONFIG_SYS_PSDPAR
 573         MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
 574 #endif
 575 #ifdef CONFIG_SYS_PASPAR
 576         MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
 577 #endif
 578 #ifdef CONFIG_SYS_PEHLPAR
 579         MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
 580 #endif
 581 #ifdef CONFIG_SYS_PQSPAR
 582         MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
 583 #endif
 584 #ifdef CONFIG_SYS_PTCPAR
 585         MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
 586 #endif
 587 #if defined(CONFIG_SYS_PORTTC)
 588         MCFGPIO_PORTTC = CONFIG_SYS_PORTTC;
 589 #endif
 590 #if defined(CONFIG_SYS_DDRTC)
 591         MCFGPIO_DDRTC  = CONFIG_SYS_DDRTC;
 592 #endif
 593 #ifdef CONFIG_SYS_PTDPAR
 594         MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
 595 #endif
 596 #ifdef CONFIG_SYS_PUAPAR
 597         MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
 598 #endif
 599
 600 #if defined(CONFIG_SYS_DDRD)
 601         MCFGPIO_DDRD = CONFIG_SYS_DDRD;
 602 #endif
 603 #ifdef CONFIG_SYS_DDRUA
 604         MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
 605 #endif
 606
 607         /* FlexBus Chipselect */
 608         init_fbcs();
 609
 610 #endif                          /* CONFIG_MONITOR_IS_IN_RAM */
 611
 612         /* defer enabling cache until boot (see do_go) */
 613         /* icache_enable(); */
 614 }
 615
 616 /*
 617  * initialize higher level parts of CPU like timers
 618  */
 619 int cpu_init_r(void)
 620 {
 621         return (0);
 622 }
 623
 624 void uart_port_conf(void)
 625 {
 626         /* Setup Ports: */
 627         switch (CONFIG_SYS_UART_PORT) {
 628         case 0:
 629                 MCFGPIO_PUAPAR &= 0xFc;
 630                 MCFGPIO_PUAPAR |= 0x03;
 631                 break;
 632         case 1:
 633                 MCFGPIO_PUAPAR &= 0xF3;
 634                 MCFGPIO_PUAPAR |= 0x0C;
 635                 break;
 636         case 2:
 637                 MCFGPIO_PASPAR &= 0xFF0F;
 638                 MCFGPIO_PASPAR |= 0x00A0;
 639                 break;
 640         }
 641 }
 642
 643 #if defined(CONFIG_CMD_NET)
 644 int fecpin_setclear(struct eth_device *dev, int setclear)
 645 {
 646         if (setclear) {
 647                 MCFGPIO_PASPAR |= 0x0F00;
 648                 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
 649         } else {
 650                 MCFGPIO_PASPAR &= 0xF0FF;
 651                 MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
 652         }
 653         return 0;
 654 }
 655 #endif                  /* CONFIG_CMD_NET */
 656 #endif
 657
 658 #if defined(CONFIG_M5249)
 659 /*
 660  * Breath some life into the CPU...
 661  *
 662  * Set up the memory map,
 663  * initialize a bunch of registers,
 664  * initialize the UPM's
 665  */
 666 void cpu_init_f(void)
 667 {
 668         /*
 669          *  NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
 670          *        (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
 671          *        which is their primary function.
 672          *        ~Jeremy
 673          */
 674         mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
 675         mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
 676         mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
 677         mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
 678         mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
 679         mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
 680
 681         /*
 682          *  dBug Compliance:
 683          *    You can verify these values by using dBug's 'ird'
 684          *    (Internal Register Display) command
 685          *    ~Jeremy
 686          *
 687          */
 688         mbar_writeByte(MCFSIM_MPARK, 0x30);     /* 5249 Internal Core takes priority over DMA */
 689         mbar_writeByte(MCFSIM_SYPCR, 0x00);
 690         mbar_writeByte(MCFSIM_SWIVR, 0x0f);
 691         mbar_writeByte(MCFSIM_SWSR, 0x00);
 692         mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
 693         mbar_writeByte(MCFSIM_SWDICR, 0x00);
 694         mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
 695         mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
 696         mbar_writeByte(MCFSIM_I2CICR, 0x00);
 697         mbar_writeByte(MCFSIM_UART1ICR, 0x00);
 698         mbar_writeByte(MCFSIM_UART2ICR, 0x00);
 699         mbar_writeByte(MCFSIM_ICR6, 0x00);
 700         mbar_writeByte(MCFSIM_ICR7, 0x00);
 701         mbar_writeByte(MCFSIM_ICR8, 0x00);
 702         mbar_writeByte(MCFSIM_ICR9, 0x00);
 703         mbar_writeByte(MCFSIM_QSPIICR, 0x00);
 704
 705         mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
 706         mbar2_writeByte(MCFSIM_INTBASE, 0x40);  /* Base interrupts at 64 */
 707         mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
 708         mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
 709
 710         /* Setup interrupt priorities for gpio7 */
 711         /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
 712
 713         /* IDE Config registers */
 714         mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
 715         mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
 716
 717         /* FlexBus Chipselect */
 718         init_fbcs();
 719
 720         /* enable instruction cache now */
 721         icache_enable();
 722 }
 723
 724 /*
 725  * initialize higher level parts of CPU like timers
 726  */
 727 int cpu_init_r(void)
 728 {
 729         return (0);
 730 }
 731
 732 void uart_port_conf(void)
 733 {
 734         /* Setup Ports: */
 735         switch (CONFIG_SYS_UART_PORT) {
 736         case 0:
 737                 break;
 738         case 1:
 739                 break;
 740         }
 741 }
 742 #endif                          /* #if defined(CONFIG_M5249) */