cpu/mcf52x2/cpu_init.c

   1 /*
   2  * (C) Copyright 2003
   3  * Josef Baumgartner <josef.baumgartner@telex.de>
   4  *
   5  * MCF5282 additionals
   6  * (C) Copyright 2005
   7  * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
   8  *
   9  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  10  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  11  * Hayden Fraser (Hayden.Fraser@freescale.com)
  12  *
  13  * MCF5275 additions
  14  * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
  15  *
  16  * See file CREDITS for list of people who contributed to this
  17  * project.
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  */
  34
  35 #include <common.h>
  36 #include <watchdog.h>
  37 #include <asm/immap.h>
  38
  39 #if defined(CONFIG_CMD_NET)
  40 #include <config.h>
  41 #include <net.h>
  42 #include <asm/fec.h>
  43 #endif
  44
  45 #ifndef CONFIG_M5272
  46 /* Only 5272 Flexbus chipselect is different from the rest */
  47 void init_fbcs(void)
  48 {
  49         volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
  50
  51 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
  52      && defined(CONFIG_SYS_CS0_CTRL))
  53         fbcs->csar0 = CONFIG_SYS_CS0_BASE;
  54         fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
  55         fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
  56 #else
  57 #warning "Chip Select 0 are not initialized/used"
  58 #endif
  59 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
  60      && defined(CONFIG_SYS_CS1_CTRL))
  61         fbcs->csar1 = CONFIG_SYS_CS1_BASE;
  62         fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
  63         fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
  64 #endif
  65 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
  66      && defined(CONFIG_SYS_CS2_CTRL))
  67         fbcs->csar2 = CONFIG_SYS_CS2_BASE;
  68         fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
  69         fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
  70 #endif
  71 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
  72      && defined(CONFIG_SYS_CS3_CTRL))
  73         fbcs->csar3 = CONFIG_SYS_CS3_BASE;
  74         fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
  75         fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
  76 #endif
  77 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
  78      && defined(CONFIG_SYS_CS4_CTRL))
  79         fbcs->csar4 = CONFIG_SYS_CS4_BASE;
  80         fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
  81         fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
  82 #endif
  83 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
  84      && defined(CONFIG_SYS_CS5_CTRL))
  85         fbcs->csar5 = CONFIG_SYS_CS5_BASE;
  86         fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
  87         fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
  88 #endif
  89 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
  90      && defined(CONFIG_SYS_CS6_CTRL))
  91         fbcs->csar6 = CONFIG_SYS_CS6_BASE;
  92         fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
  93         fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
  94 #endif
  95 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
  96      && defined(CONFIG_SYS_CS7_CTRL))
  97         fbcs->csar7 = CONFIG_SYS_CS7_BASE;
  98         fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
  99         fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
 100 #endif
 101 }
 102 #endif
 103
 104 #if defined(CONFIG_M5208)
 105 void cpu_init_f(void)
 106 {
 107         volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
 108
 109 #ifndef CONFIG_WATCHDOG
 110         volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
 111
 112         /* Disable the watchdog if we aren't using it */
 113         wdg->cr = 0;
 114 #endif
 115
 116         scm1->mpr = 0x77777777;
 117         scm1->pacra = 0;
 118         scm1->pacrb = 0;
 119         scm1->pacrc = 0;
 120         scm1->pacrd = 0;
 121         scm1->pacre = 0;
 122         scm1->pacrf = 0;
 123
 124         /* FlexBus Chipselect */
 125         init_fbcs();
 126
 127         icache_enable();
 128 }
 129
 130 /* initialize higher level parts of CPU like timers */
 131 int cpu_init_r(void)
 132 {
 133         return (0);
 134 }
 135
 136 void uart_port_conf(void)
 137 {
 138         volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 139
 140         /* Setup Ports: */
 141         switch (CONFIG_SYS_UART_PORT) {
 142         case 0:
 143                 gpio->par_uart &= GPIO_PAR_UART0_MASK;
 144                 gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
 145                 break;
 146         case 1:
 147                 gpio->par_uart &= GPIO_PAR_UART0_MASK;
 148                 gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
 149                 break;
 150         case 2:
 151 #ifdef CONFIG_SYS_UART2_PRI_GPIO
 152                 gpio->par_timer &=
 153                     (GPIO_PAR_TMR_TIN0_MASK | GPIO_PAR_TMR_TIN1_MASK);
 154                 gpio->par_timer |=
 155                     (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
 156 #endif
 157 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
 158                 gpio->par_feci2c &=
 159                     (GPIO_PAR_FECI2C_MDC_MASK | GPIO_PAR_FECI2C_MDIO_MASK);
 160                 gpio->par_feci2c |=
 161                     (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
 162 #endif
 163 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
 164                 gpio->par_feci2c &=
 165                     (GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
 166                 gpio->par_feci2c |=
 167                     (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
 168 #endif
 169                 break;
 170         }
 171 }
 172
 173 #if defined(CONFIG_CMD_NET)
 174 int fecpin_setclear(struct eth_device *dev, int setclear)
 175 {
 176         volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 177
 178         if (setclear) {
 179                 gpio->par_fec |=
 180                     GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
 181                 gpio->par_feci2c |=
 182                     GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
 183         } else {
 184                 gpio->par_fec &=
 185                     (GPIO_PAR_FEC_7W_MASK & GPIO_PAR_FEC_MII_MASK);
 186                 gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_MASK;
 187         }
 188         return 0;
 189 }
 190 #endif                          /* CONFIG_CMD_NET */
 191 #endif                          /* CONFIG_M5208 */
 192
 193 #if defined(CONFIG_M5253)
 194 /*
 195  * Breath some life into the CPU...
 196  *
 197  * Set up the memory map,
 198  * initialize a bunch of registers,
 199  * initialize the UPM's
 200  */
 201 void cpu_init_f(void)
 202 {
 203         mbar_writeByte(MCFSIM_MPARK, 0x40);     /* 5249 Internal Core takes priority over DMA */
 204         mbar_writeByte(MCFSIM_SYPCR, 0x00);
 205         mbar_writeByte(MCFSIM_SWIVR, 0x0f);
 206         mbar_writeByte(MCFSIM_SWSR, 0x00);
 207         mbar_writeByte(MCFSIM_SWDICR, 0x00);
 208         mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
 209         mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
 210         mbar_writeByte(MCFSIM_I2CICR, 0x00);
 211         mbar_writeByte(MCFSIM_UART1ICR, 0x00);
 212         mbar_writeByte(MCFSIM_UART2ICR, 0x00);
 213         mbar_writeByte(MCFSIM_ICR6, 0x00);
 214         mbar_writeByte(MCFSIM_ICR7, 0x00);
 215         mbar_writeByte(MCFSIM_ICR8, 0x00);
 216         mbar_writeByte(MCFSIM_ICR9, 0x00);
 217         mbar_writeByte(MCFSIM_QSPIICR, 0x00);
 218
 219         mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
 220         mbar2_writeByte(MCFSIM_INTBASE, 0x40);  /* Base interrupts at 64 */
 221         mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
 222
 223         /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
 224
 225         /* FlexBus Chipselect */
 226         init_fbcs();
 227
 228 #ifdef CONFIG_FSL_I2C
 229         CONFIG_SYS_I2C_PINMUX_REG =
 230             CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
 231         CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
 232 #ifdef CONFIG_SYS_I2C2_OFFSET
 233         CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
 234         CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
 235 #endif
 236 #endif
 237
 238         /* enable instruction cache now */
 239         icache_enable();
 240 }
 241
 242 /*initialize higher level parts of CPU like timers */
 243 int cpu_init_r(void)
 244 {
 245         return (0);
 246 }
 247
 248 void uart_port_conf(void)
 249 {
 250         /* Setup Ports: */
 251         switch (CONFIG_SYS_UART_PORT) {
 252         case 0:
 253                 break;
 254         case 1:
 255                 break;
 256         case 2:
 257                 break;
 258         }
 259 }
 260 #endif                          /* #if defined(CONFIG_M5253) */
 261
 262 #if defined(CONFIG_M5271)
 263 void cpu_init_f(void)
 264 {
 265 #ifndef CONFIG_WATCHDOG
 266         /* Disable the watchdog if we aren't using it */
 267         mbar_writeShort(MCF_WTM_WCR, 0);
 268 #endif
 269
 270         /* FlexBus Chipselect */
 271         init_fbcs();
 272
 273 #ifdef CONFIG_SYS_MCF_SYNCR
 274         /* Set clockspeed according to board header file */
 275         mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
 276 #else
 277         /* Set clockspeed to 100MHz */
 278         mbar_writeLong(MCF_FMPLL_SYNCR,
 279                         MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
 280 #endif
 281         while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
 282 }
 283
 284 /*
 285  * initialize higher level parts of CPU like timers
 286  */
 287 int cpu_init_r(void)
 288 {
 289         return (0);
 290 }
 291
 292 void uart_port_conf(void)
 293 {
 294         /* Setup Ports: */
 295         switch (CONFIG_SYS_UART_PORT) {
 296         case 0:
 297                 mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
 298                                 MCF_GPIO_PAR_UART_U0RXD);
 299                 break;
 300         case 1:
 301                 mbar_writeShort(MCF_GPIO_PAR_UART,
 302                                 MCF_GPIO_PAR_UART_U1RXD_UART1 |
 303                                 MCF_GPIO_PAR_UART_U1TXD_UART1);
 304                 break;
 305         case 2:
 306                 mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
 307                 break;
 308         }
 309 }
 310
 311 #if defined(CONFIG_CMD_NET)
 312 int fecpin_setclear(struct eth_device *dev, int setclear)
 313 {
 314         if (setclear) {
 315                 /* Enable Ethernet pins */
 316                 mbar_writeByte(MCF_GPIO_PAR_FECI2C,
 317                                (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
 318         } else {
 319         }
 320
 321         return 0;
 322 }
 323 #endif                          /* CONFIG_CMD_NET */
 324 #endif
 325
 326 #if defined(CONFIG_M5272)
 327 /*
 328  * Breath some life into the CPU...
 329  *
 330  * Set up the memory map,
 331  * initialize a bunch of registers,
 332  * initialize the UPM's
 333  */
 334 void cpu_init_f(void)
 335 {
 336         /* if we come from RAM we assume the CPU is
 337          * already initialized.
 338          */
 339 #ifndef CONFIG_MONITOR_IS_IN_RAM
 340         volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
 341         volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
 342         volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
 343
 344         sysctrl->sc_scr = CONFIG_SYS_SCR;
 345         sysctrl->sc_spr = CONFIG_SYS_SPR;
 346
 347         /* Setup Ports: */
 348         gpio->gpio_pacnt = CONFIG_SYS_PACNT;
 349         gpio->gpio_paddr = CONFIG_SYS_PADDR;
 350         gpio->gpio_padat = CONFIG_SYS_PADAT;
 351         gpio->gpio_pbcnt = CONFIG_SYS_PBCNT;
 352         gpio->gpio_pbddr = CONFIG_SYS_PBDDR;
 353         gpio->gpio_pbdat = CONFIG_SYS_PBDAT;
 354         gpio->gpio_pdcnt = CONFIG_SYS_PDCNT;
 355
 356         /* Memory Controller: */
 357         csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM;
 358         csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM;
 359
 360 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
 361         csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM;
 362         csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM;
 363 #endif
 364
 365 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 366         csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM;
 367         csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM;
 368 #endif
 369
 370 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
 371         csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM;
 372         csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM;
 373 #endif
 374
 375 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
 376         csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM;
 377         csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM;
 378 #endif
 379
 380 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
 381         csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM;
 382         csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM;
 383 #endif
 384
 385 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
 386         csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM;
 387         csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM;
 388 #endif
 389
 390 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
 391         csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM;
 392         csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM;
 393 #endif
 394
 395 #endif                          /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
 396
 397         /* enable instruction cache now */
 398         icache_enable();
 399
 400 }
 401
 402 /*
 403  * initialize higher level parts of CPU like timers
 404  */
 405 int cpu_init_r(void)
 406 {
 407         return (0);
 408 }
 409
 410 void uart_port_conf(void)
 411 {
 412         volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 413
 414         /* Setup Ports: */
 415         switch (CONFIG_SYS_UART_PORT) {
 416         case 0:
 417                 gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
 418                 gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
 419                 break;
 420         case 1:
 421                 gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
 422                 gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
 423                 break;
 424         }
 425 }
 426
 427 #if defined(CONFIG_CMD_NET)
 428 int fecpin_setclear(struct eth_device *dev, int setclear)
 429 {
 430         volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 431
 432         if (setclear) {
 433                 gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
 434                                     GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
 435                                     GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
 436                                     GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
 437         } else {
 438         }
 439         return 0;
 440 }
 441 #endif                          /* CONFIG_CMD_NET */
 442 #endif                          /* #if defined(CONFIG_M5272) */
 443
 444 #if defined(CONFIG_M5275)
 445
 446 /*
 447  * Breathe some life into the CPU...
 448  *
 449  * Set up the memory map,
 450  * initialize a bunch of registers,
 451  * initialize the UPM's
 452  */
 453 void cpu_init_f(void)
 454 {
 455         /*
 456          * if we come from RAM we assume the CPU is
 457          * already initialized.
 458          */
 459
 460 #ifndef CONFIG_MONITOR_IS_IN_RAM
 461         volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
 462         volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
 463
 464         /* Kill watchdog so we can initialize the PLL */
 465         wdog_reg->wcr = 0;
 466
 467         /* FlexBus Chipselect */
 468         init_fbcs();
 469 #endif                          /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
 470
 471 #ifdef CONFIG_FSL_I2C
 472         CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
 473         CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
 474 #endif
 475
 476         /* enable instruction cache now */
 477         icache_enable();
 478 }
 479
 480 /*
 481  * initialize higher level parts of CPU like timers
 482  */
 483 int cpu_init_r(void)
 484 {
 485         return (0);
 486 }
 487
 488 void uart_port_conf(void)
 489 {
 490         volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 491
 492         /* Setup Ports: */
 493         switch (CONFIG_SYS_UART_PORT) {
 494         case 0:
 495                 gpio->par_uart |= UART0_ENABLE_MASK;
 496                 break;
 497         case 1:
 498                 gpio->par_uart |= UART1_ENABLE_MASK;
 499                 break;
 500         case 2:
 501                 gpio->par_uart |= UART2_ENABLE_MASK;
 502                 break;
 503         }
 504 }
 505
 506 #if defined(CONFIG_CMD_NET)
 507 int fecpin_setclear(struct eth_device *dev, int setclear)
 508 {
 509         struct fec_info_s *info = (struct fec_info_s *) dev->priv;
 510         volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
 511
 512         if (setclear) {
 513                 /* Enable Ethernet pins */
 514                 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
 515                         gpio->par_feci2c |= 0x0F00;
 516                         gpio->par_fec0hl |= 0xC0;
 517                 } else {
 518                         gpio->par_feci2c |= 0x00A0;
 519                         gpio->par_fec1hl |= 0xC0;
 520                 }
 521         } else {
 522                 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
 523                         gpio->par_feci2c &= ~0x0F00;
 524                         gpio->par_fec0hl &= ~0xC0;
 525                 } else {
 526                         gpio->par_feci2c &= ~0x00A0;
 527                         gpio->par_fec1hl &= ~0xC0;
 528                 }
 529         }
 530
 531         return 0;
 532 }
 533 #endif                          /* CONFIG_CMD_NET */
 534 #endif                          /* #if defined(CONFIG_M5275) */
 535
 536 #if defined(CONFIG_M5282)
 537 /*
 538  * Breath some life into the CPU...
 539  *
 540  * Set up the memory map,
 541  * initialize a bunch of registers,
 542  * initialize the UPM's
 543  */
 544 void cpu_init_f(void)
 545 {
 546 #ifndef CONFIG_WATCHDOG
 547         /* disable watchdog if we aren't using it */
 548         MCFWTM_WCR = 0;
 549 #endif
 550
 551 #ifndef CONFIG_MONITOR_IS_IN_RAM
 552         /* Set speed /PLL */
 553         MCFCLOCK_SYNCR =
 554             MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
 555             MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
 556         while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
 557
 558         MCFGPIO_PBCDPAR = 0xc0;
 559
 560         /* Set up the GPIO ports */
 561 #ifdef CONFIG_SYS_PEPAR
 562         MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
 563 #endif
 564 #ifdef  CONFIG_SYS_PFPAR
 565         MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
 566 #endif
 567 #ifdef CONFIG_SYS_PJPAR
 568         MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
 569 #endif
 570 #ifdef CONFIG_SYS_PSDPAR
 571         MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
 572 #endif
 573 #ifdef CONFIG_SYS_PASPAR
 574         MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
 575 #endif
 576 #ifdef CONFIG_SYS_PEHLPAR
 577         MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
 578 #endif
 579 #ifdef CONFIG_SYS_PQSPAR
 580         MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
 581 #endif
 582 #ifdef CONFIG_SYS_PTCPAR
 583         MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
 584 #endif
 585 #ifdef CONFIG_SYS_PTDPAR
 586         MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
 587 #endif
 588 #ifdef CONFIG_SYS_PUAPAR
 589         MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
 590 #endif
 591
 592 #ifdef CONFIG_SYS_DDRUA
 593         MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
 594 #endif
 595
 596         /* FlexBus Chipselect */
 597         init_fbcs();
 598
 599 #endif                          /* CONFIG_MONITOR_IS_IN_RAM */
 600
 601         /* defer enabling cache until boot (see do_go) */
 602         /* icache_enable(); */
 603 }
 604
 605 /*
 606  * initialize higher level parts of CPU like timers
 607  */
 608 int cpu_init_r(void)
 609 {
 610         return (0);
 611 }
 612
 613 void uart_port_conf(void)
 614 {
 615         /* Setup Ports: */
 616         switch (CONFIG_SYS_UART_PORT) {
 617         case 0:
 618                 MCFGPIO_PUAPAR &= 0xFc;
 619                 MCFGPIO_PUAPAR |= 0x03;
 620                 break;
 621         case 1:
 622                 MCFGPIO_PUAPAR &= 0xF3;
 623                 MCFGPIO_PUAPAR |= 0x0C;
 624                 break;
 625         case 2:
 626                 MCFGPIO_PASPAR &= 0xFF0F;
 627                 MCFGPIO_PASPAR |= 0x00A0;
 628                 break;
 629         }
 630 }
 631
 632 #if defined(CONFIG_CMD_NET)
 633 int fecpin_setclear(struct eth_device *dev, int setclear)
 634 {
 635         if (setclear) {
 636                 MCFGPIO_PASPAR |= 0x0F00;
 637                 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
 638         } else {
 639                 MCFGPIO_PASPAR &= 0xF0FF;
 640                 MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
 641         }
 642         return 0;
 643 }
 644 #endif                  /* CONFIG_CMD_NET */
 645 #endif
 646
 647 #if defined(CONFIG_M5249)
 648 /*
 649  * Breath some life into the CPU...
 650  *
 651  * Set up the memory map,
 652  * initialize a bunch of registers,
 653  * initialize the UPM's
 654  */
 655 void cpu_init_f(void)
 656 {
 657         /*
 658          *  NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
 659          *        (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
 660          *        which is their primary function.
 661          *        ~Jeremy
 662          */
 663         mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
 664         mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
 665         mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
 666         mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
 667         mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
 668         mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
 669
 670         /*
 671          *  dBug Compliance:
 672          *    You can verify these values by using dBug's 'ird'
 673          *    (Internal Register Display) command
 674          *    ~Jeremy
 675          *
 676          */
 677         mbar_writeByte(MCFSIM_MPARK, 0x30);     /* 5249 Internal Core takes priority over DMA */
 678         mbar_writeByte(MCFSIM_SYPCR, 0x00);
 679         mbar_writeByte(MCFSIM_SWIVR, 0x0f);
 680         mbar_writeByte(MCFSIM_SWSR, 0x00);
 681         mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
 682         mbar_writeByte(MCFSIM_SWDICR, 0x00);
 683         mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
 684         mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
 685         mbar_writeByte(MCFSIM_I2CICR, 0x00);
 686         mbar_writeByte(MCFSIM_UART1ICR, 0x00);
 687         mbar_writeByte(MCFSIM_UART2ICR, 0x00);
 688         mbar_writeByte(MCFSIM_ICR6, 0x00);
 689         mbar_writeByte(MCFSIM_ICR7, 0x00);
 690         mbar_writeByte(MCFSIM_ICR8, 0x00);
 691         mbar_writeByte(MCFSIM_ICR9, 0x00);
 692         mbar_writeByte(MCFSIM_QSPIICR, 0x00);
 693
 694         mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
 695         mbar2_writeByte(MCFSIM_INTBASE, 0x40);  /* Base interrupts at 64 */
 696         mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
 697         mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
 698
 699         /* Setup interrupt priorities for gpio7 */
 700         /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
 701
 702         /* IDE Config registers */
 703         mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
 704         mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
 705
 706         /* FlexBus Chipselect */
 707         init_fbcs();
 708
 709         /* enable instruction cache now */
 710         icache_enable();
 711 }
 712
 713 /*
 714  * initialize higher level parts of CPU like timers
 715  */
 716 int cpu_init_r(void)
 717 {
 718         return (0);
 719 }
 720
 721 void uart_port_conf(void)
 722 {
 723         /* Setup Ports: */
 724         switch (CONFIG_SYS_UART_PORT) {
 725         case 0:
 726                 break;
 727         case 1:
 728                 break;
 729         }
 730 }
 731 #endif                          /* #if defined(CONFIG_M5249) */