3 * Josef Baumgartner <josef.baumgartner@telex.de>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/m5271.h>
29 #include <asm/immap_5271.h>
33 #include <asm/m5272.h>
34 #include <asm/immap_5272.h>
38 #include <asm/m5282.h>
39 #include <asm/immap_5282.h>
43 #include <asm/m5249.h>
46 #if defined(CONFIG_M5271)
47 void cpu_init_f (void)
49 #ifndef CONFIG_WATCHDOG
50 /* Disable the watchdog if we aren't using it */
51 mbar_writeShort(MCF_WTM_WCR
, 0);
54 /* Set clockspeed to 100MHz */
55 mbar_writeShort(MCF_FMPLL_SYNCR
,
56 MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
57 while (!mbar_readByte(MCF_FMPLL_SYNSR
) & MCF_FMPLL_SYNSR_LOCK
);
59 /* Enable UART pins */
60 mbar_writeShort(MCF_GPIO_PAR_UART
, MCF_GPIO_PAR_UART_U0TXD
|
61 MCF_GPIO_PAR_UART_U0RXD
|
62 MCF_GPIO_PAR_UART_U1RXD_UART1
|
63 MCF_GPIO_PAR_UART_U1TXD_UART1
);
65 /* Enable Ethernet pins */
66 mbar_writeByte(MCF_GPIO_PAR_FECI2C
, CFG_FECI2C
);
70 * initialize higher level parts of CPU like timers
78 #if defined(CONFIG_M5272)
80 * Breath some life into the CPU...
82 * Set up the memory map,
83 * initialize a bunch of registers,
84 * initialize the UPM's
86 void cpu_init_f (void)
88 /* if we come from RAM we assume the CPU is
89 * already initialized.
91 #ifndef CONFIG_MONITOR_IS_IN_RAM
92 volatile immap_t
*regp
= (immap_t
*)CFG_MBAR
;
94 volatile unsigned char *mbar
;
95 mbar
= (volatile unsigned char *) CFG_MBAR
;
97 regp
->sysctrl_reg
.sc_scr
= CFG_SCR
;
98 regp
->sysctrl_reg
.sc_spr
= CFG_SPR
;
101 regp
->gpio_reg
.gpio_pacnt
= CFG_PACNT
;
102 regp
->gpio_reg
.gpio_paddr
= CFG_PADDR
;
103 regp
->gpio_reg
.gpio_padat
= CFG_PADAT
;
104 regp
->gpio_reg
.gpio_pbcnt
= CFG_PBCNT
;
105 regp
->gpio_reg
.gpio_pbddr
= CFG_PBDDR
;
106 regp
->gpio_reg
.gpio_pbdat
= CFG_PBDAT
;
107 regp
->gpio_reg
.gpio_pdcnt
= CFG_PDCNT
;
109 /* Memory Controller: */
110 regp
->csctrl_reg
.cs_br0
= CFG_BR0_PRELIM
;
111 regp
->csctrl_reg
.cs_or0
= CFG_OR0_PRELIM
;
113 #if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
114 regp
->csctrl_reg
.cs_br1
= CFG_BR1_PRELIM
;
115 regp
->csctrl_reg
.cs_or1
= CFG_OR1_PRELIM
;
118 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
119 regp
->csctrl_reg
.cs_br2
= CFG_BR2_PRELIM
;
120 regp
->csctrl_reg
.cs_or2
= CFG_OR2_PRELIM
;
123 #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
124 regp
->csctrl_reg
.cs_br3
= CFG_BR3_PRELIM
;
125 regp
->csctrl_reg
.cs_or3
= CFG_OR3_PRELIM
;
128 #if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
129 regp
->csctrl_reg
.cs_br4
= CFG_BR4_PRELIM
;
130 regp
->csctrl_reg
.cs_or4
= CFG_OR4_PRELIM
;
133 #if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
134 regp
->csctrl_reg
.cs_br5
= CFG_BR5_PRELIM
;
135 regp
->csctrl_reg
.cs_or5
= CFG_OR5_PRELIM
;
138 #if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
139 regp
->csctrl_reg
.cs_br6
= CFG_BR6_PRELIM
;
140 regp
->csctrl_reg
.cs_or6
= CFG_OR6_PRELIM
;
143 #if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
144 regp
->csctrl_reg
.cs_br7
= CFG_BR7_PRELIM
;
145 regp
->csctrl_reg
.cs_or7
= CFG_OR7_PRELIM
;
148 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
150 /* enable instruction cache now */
156 * initialize higher level parts of CPU like timers
158 int cpu_init_r (void)
162 #endif /* #if defined(CONFIG_M5272) */
167 * Breath some life into the CPU...
169 * Set up the memory map,
170 * initialize a bunch of registers,
171 * initialize the UPM's
173 void cpu_init_f (void)
179 * initialize higher level parts of CPU like timers
181 int cpu_init_r (void)
187 #if defined(CONFIG_M5249)
189 * Breath some life into the CPU...
191 * Set up the memory map,
192 * initialize a bunch of registers,
193 * initialize the UPM's
195 void cpu_init_f (void)
197 #ifndef CFG_PLL_BYPASS
199 * Setup the PLL to run at the specified speed
202 volatile unsigned long cpll
= mbar2_readLong(MCFSIM_PLLCR
);
205 pllcr
= 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
207 pllcr
= 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
209 cpll
= cpll
& 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
210 mbar2_writeLong(MCFSIM_PLLCR
, cpll
); /* Set the PLL to bypass mode (PSTCLK = crystal) */
211 mbar2_writeLong(MCFSIM_PLLCR
, pllcr
); /* set the clock speed */
212 pllcr
^= 0x00000001; /* Set pll bypass to 1 */
213 mbar2_writeLong(MCFSIM_PLLCR
, pllcr
); /* Start locking (pll bypass = 1) */
214 udelay(0x20); /* Wait for a lock ... */
215 #endif /* #ifndef CFG_PLL_BYPASS */
218 * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
219 * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
220 * which is their primary function.
223 mbar2_writeLong(MCFSIM_GPIO_FUNC
, CFG_GPIO_FUNC
);
224 mbar2_writeLong(MCFSIM_GPIO1_FUNC
, CFG_GPIO1_FUNC
);
225 mbar2_writeLong(MCFSIM_GPIO_EN
, CFG_GPIO_EN
);
226 mbar2_writeLong(MCFSIM_GPIO1_EN
, CFG_GPIO1_EN
);
227 mbar2_writeLong(MCFSIM_GPIO_OUT
, CFG_GPIO_OUT
);
228 mbar2_writeLong(MCFSIM_GPIO1_OUT
, CFG_GPIO1_OUT
);
232 * You can verify these values by using dBug's 'ird'
233 * (Internal Register Display) command
237 mbar_writeByte(MCFSIM_MPARK
, 0x30); /* 5249 Internal Core takes priority over DMA */
238 mbar_writeByte(MCFSIM_SYPCR
, 0x00);
239 mbar_writeByte(MCFSIM_SWIVR
, 0x0f);
240 mbar_writeByte(MCFSIM_SWSR
, 0x00);
241 mbar_writeLong(MCFSIM_IMR
, 0xfffffbff);
242 mbar_writeByte(MCFSIM_SWDICR
, 0x00);
243 mbar_writeByte(MCFSIM_TIMER1ICR
, 0x00);
244 mbar_writeByte(MCFSIM_TIMER2ICR
, 0x88);
245 mbar_writeByte(MCFSIM_I2CICR
, 0x00);
246 mbar_writeByte(MCFSIM_UART1ICR
, 0x00);
247 mbar_writeByte(MCFSIM_UART2ICR
, 0x00);
248 mbar_writeByte(MCFSIM_ICR6
, 0x00);
249 mbar_writeByte(MCFSIM_ICR7
, 0x00);
250 mbar_writeByte(MCFSIM_ICR8
, 0x00);
251 mbar_writeByte(MCFSIM_ICR9
, 0x00);
252 mbar_writeByte(MCFSIM_QSPIICR
, 0x00);
254 mbar2_writeLong(MCFSIM_GPIO_INT_EN
, 0x00000080);
255 mbar2_writeByte(MCFSIM_INTBASE
, 0x40); /* Base interrupts at 64 */
256 mbar2_writeByte(MCFSIM_SPURVEC
, 0x00);
257 mbar2_writeLong(MCFSIM_IDECONFIG1
, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
259 /* Setup interrupt priorities for gpio7 */
260 /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
262 /* IDE Config registers */
263 mbar2_writeLong(MCFSIM_IDECONFIG1
, 0x00000020);
264 mbar2_writeLong(MCFSIM_IDECONFIG2
, 0x00000000);
267 * Setup chip selects...
270 mbar_writeShort(MCFSIM_CSAR1
, CFG_CSAR1
);
271 mbar_writeShort(MCFSIM_CSCR1
, CFG_CSCR1
);
272 mbar_writeLong(MCFSIM_CSMR1
, CFG_CSMR1
);
274 mbar_writeShort(MCFSIM_CSAR0
, CFG_CSAR0
);
275 mbar_writeShort(MCFSIM_CSCR0
, CFG_CSCR0
);
276 mbar_writeLong(MCFSIM_CSMR0
, CFG_CSMR0
);
278 /* enable instruction cache now */
283 * initialize higher level parts of CPU like timers
285 int cpu_init_r (void)
289 #endif /* #if defined(CONFIG_M5249) */