3 * Josef Baumgartner <josef.baumgartner@telex.de>
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
9 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
10 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
11 * Hayden Fraser (Hayden.Fraser@freescale.com)
14 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #include <asm/immap.h>
39 #if defined(CONFIG_M5253)
41 * Breath some life into the CPU...
43 * Set up the memory map,
44 * initialize a bunch of registers,
45 * initialize the UPM's
49 mbar_writeByte(MCFSIM_MPARK
, 0x40); /* 5249 Internal Core takes priority over DMA */
50 mbar_writeByte(MCFSIM_SYPCR
, 0x00);
51 mbar_writeByte(MCFSIM_SWIVR
, 0x0f);
52 mbar_writeByte(MCFSIM_SWSR
, 0x00);
53 mbar_writeByte(MCFSIM_SWDICR
, 0x00);
54 mbar_writeByte(MCFSIM_TIMER1ICR
, 0x00);
55 mbar_writeByte(MCFSIM_TIMER2ICR
, 0x88);
56 mbar_writeByte(MCFSIM_I2CICR
, 0x00);
57 mbar_writeByte(MCFSIM_UART1ICR
, 0x00);
58 mbar_writeByte(MCFSIM_UART2ICR
, 0x00);
59 mbar_writeByte(MCFSIM_ICR6
, 0x00);
60 mbar_writeByte(MCFSIM_ICR7
, 0x00);
61 mbar_writeByte(MCFSIM_ICR8
, 0x00);
62 mbar_writeByte(MCFSIM_ICR9
, 0x00);
63 mbar_writeByte(MCFSIM_QSPIICR
, 0x00);
65 mbar2_writeLong(MCFSIM_GPIO_INT_EN
, 0x00000080);
66 mbar2_writeByte(MCFSIM_INTBASE
, 0x40); /* Base interrupts at 64 */
67 mbar2_writeByte(MCFSIM_SPURVEC
, 0x00);
69 /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
72 * Setup chip selects...
75 mbar_writeShort(MCFSIM_CSAR1
, CFG_CSAR1
);
76 mbar_writeShort(MCFSIM_CSCR1
, CFG_CSCR1
);
77 mbar_writeLong(MCFSIM_CSMR1
, CFG_CSMR1
);
79 mbar_writeShort(MCFSIM_CSAR0
, CFG_CSAR0
);
80 mbar_writeShort(MCFSIM_CSCR0
, CFG_CSCR0
);
81 mbar_writeLong(MCFSIM_CSMR0
, CFG_CSMR0
);
84 CFG_I2C_PINMUX_REG
= CFG_I2C_PINMUX_REG
& CFG_I2C_PINMUX_CLR
;
85 CFG_I2C_PINMUX_REG
|= CFG_I2C_PINMUX_SET
;
86 #ifdef CFG_I2C2_OFFSET
87 CFG_I2C2_PINMUX_REG
&= CFG_I2C2_PINMUX_CLR
;
88 CFG_I2C2_PINMUX_REG
|= CFG_I2C2_PINMUX_SET
;
92 /* enable instruction cache now */
96 /*initialize higher level parts of CPU like timers */
102 void uart_port_conf(void)
105 switch (CFG_UART_PORT
) {
114 #endif /* #if defined(CONFIG_M5253) */
116 #if defined(CONFIG_M5271)
117 void cpu_init_f(void)
119 #ifndef CONFIG_WATCHDOG
120 /* Disable the watchdog if we aren't using it */
121 mbar_writeShort(MCF_WTM_WCR
, 0);
124 /* Set clockspeed to 100MHz */
125 mbar_writeShort(MCF_FMPLL_SYNCR
,
126 MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
127 while (!mbar_readByte(MCF_FMPLL_SYNSR
) & MCF_FMPLL_SYNSR_LOCK
) ;
131 * initialize higher level parts of CPU like timers
138 void uart_port_conf(void)
141 switch (CFG_UART_PORT
) {
143 mbar_writeShort(MCF_GPIO_PAR_UART
, MCF_GPIO_PAR_UART_U0TXD
|
144 MCF_GPIO_PAR_UART_U0RXD
);
147 mbar_writeShort(MCF_GPIO_PAR_UART
,
148 MCF_GPIO_PAR_UART_U1RXD_UART1
|
149 MCF_GPIO_PAR_UART_U1TXD_UART1
);
152 mbar_writeShort(MCF_GPIO_PAR_UART
, 0x3000);
158 #if defined(CONFIG_M5272)
160 * Breath some life into the CPU...
162 * Set up the memory map,
163 * initialize a bunch of registers,
164 * initialize the UPM's
166 void cpu_init_f(void)
168 /* if we come from RAM we assume the CPU is
169 * already initialized.
171 #ifndef CONFIG_MONITOR_IS_IN_RAM
172 volatile sysctrl_t
*sysctrl
= (sysctrl_t
*) (CFG_MBAR
);
173 volatile gpio_t
*gpio
= (gpio_t
*) (MMAP_GPIO
);
174 volatile csctrl_t
*csctrl
= (csctrl_t
*) (MMAP_FBCS
);
176 sysctrl
->sc_scr
= CFG_SCR
;
177 sysctrl
->sc_spr
= CFG_SPR
;
180 gpio
->gpio_pacnt
= CFG_PACNT
;
181 gpio
->gpio_paddr
= CFG_PADDR
;
182 gpio
->gpio_padat
= CFG_PADAT
;
183 gpio
->gpio_pbcnt
= CFG_PBCNT
;
184 gpio
->gpio_pbddr
= CFG_PBDDR
;
185 gpio
->gpio_pbdat
= CFG_PBDAT
;
186 gpio
->gpio_pdcnt
= CFG_PDCNT
;
188 /* Memory Controller: */
189 csctrl
->cs_br0
= CFG_BR0_PRELIM
;
190 csctrl
->cs_or0
= CFG_OR0_PRELIM
;
192 #if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
193 csctrl
->cs_br1
= CFG_BR1_PRELIM
;
194 csctrl
->cs_or1
= CFG_OR1_PRELIM
;
197 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
198 csctrl
->cs_br2
= CFG_BR2_PRELIM
;
199 csctrl
->cs_or2
= CFG_OR2_PRELIM
;
202 #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
203 csctrl
->cs_br3
= CFG_BR3_PRELIM
;
204 csctrl
->cs_or3
= CFG_OR3_PRELIM
;
207 #if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
208 csctrl
->cs_br4
= CFG_BR4_PRELIM
;
209 csctrl
->cs_or4
= CFG_OR4_PRELIM
;
212 #if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
213 csctrl
->cs_br5
= CFG_BR5_PRELIM
;
214 csctrl
->cs_or5
= CFG_OR5_PRELIM
;
217 #if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
218 csctrl
->cs_br6
= CFG_BR6_PRELIM
;
219 csctrl
->cs_or6
= CFG_OR6_PRELIM
;
222 #if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
223 csctrl
->cs_br7
= CFG_BR7_PRELIM
;
224 csctrl
->cs_or7
= CFG_OR7_PRELIM
;
227 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
229 /* enable instruction cache now */
235 * initialize higher level parts of CPU like timers
242 void uart_port_conf(void)
244 volatile gpio_t
*gpio
= (gpio_t
*) MMAP_GPIO
;
247 switch (CFG_UART_PORT
) {
249 gpio
->gpio_pbcnt
&= ~(GPIO_PBCNT_PB0MSK
| GPIO_PBCNT_PB1MSK
);
250 gpio
->gpio_pbcnt
|= (GPIO_PBCNT_URT0_TXD
| GPIO_PBCNT_URT0_RXD
);
253 gpio
->gpio_pdcnt
&= ~(GPIO_PDCNT_PD1MSK
| GPIO_PDCNT_PD4MSK
);
254 gpio
->gpio_pdcnt
|= (GPIO_PDCNT_URT1_RXD
| GPIO_PDCNT_URT1_TXD
);
258 #endif /* #if defined(CONFIG_M5272) */
260 #if defined(CONFIG_M5275)
263 * Breathe some life into the CPU...
265 * Set up the memory map,
266 * initialize a bunch of registers,
267 * initialize the UPM's
269 void cpu_init_f(void)
271 /* if we come from RAM we assume the CPU is
272 * already initialized.
275 #ifndef CONFIG_MONITOR_IS_IN_RAM
276 volatile wdog_t
*wdog_reg
= (wdog_t
*)(MMAP_WDOG
);
277 volatile gpio_t
*gpio_reg
= (gpio_t
*)(MMAP_GPIO
);
278 volatile csctrl_t
*csctrl_reg
= (csctrl_t
*)(MMAP_FBCS
);
280 /* Kill watchdog so we can initialize the PLL */
283 /* Memory Controller: */
285 csctrl_reg
->ar0
= CFG_AR0_PRELIM
;
286 csctrl_reg
->cr0
= CFG_CR0_PRELIM
;
287 csctrl_reg
->mr0
= CFG_MR0_PRELIM
;
289 #if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM))
290 csctrl_reg
->ar1
= CFG_AR1_PRELIM
;
291 csctrl_reg
->cr1
= CFG_CR1_PRELIM
;
292 csctrl_reg
->mr1
= CFG_MR1_PRELIM
;
295 #if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM))
296 csctrl_reg
->ar2
= CFG_AR2_PRELIM
;
297 csctrl_reg
->cr2
= CFG_CR2_PRELIM
;
298 csctrl_reg
->mr2
= CFG_MR2_PRELIM
;
301 #if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM))
302 csctrl_reg
->ar3
= CFG_AR3_PRELIM
;
303 csctrl_reg
->cr3
= CFG_CR3_PRELIM
;
304 csctrl_reg
->mr3
= CFG_MR3_PRELIM
;
307 #if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM))
308 csctrl_reg
->ar4
= CFG_AR4_PRELIM
;
309 csctrl_reg
->cr4
= CFG_CR4_PRELIM
;
310 csctrl_reg
->mr4
= CFG_MR4_PRELIM
;
313 #if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM))
314 csctrl_reg
->ar5
= CFG_AR5_PRELIM
;
315 csctrl_reg
->cr5
= CFG_CR5_PRELIM
;
316 csctrl_reg
->mr5
= CFG_MR5_PRELIM
;
319 #if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM))
320 csctrl_reg
->ar6
= CFG_AR6_PRELIM
;
321 csctrl_reg
->cr6
= CFG_CR6_PRELIM
;
322 csctrl_reg
->mr6
= CFG_MR6_PRELIM
;
325 #if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM))
326 csctrl_reg
->ar7
= CFG_AR7_PRELIM
;
327 csctrl_reg
->cr7
= CFG_CR7_PRELIM
;
328 csctrl_reg
->mr7
= CFG_MR7_PRELIM
;
331 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
333 #ifdef CONFIG_FSL_I2C
334 CFG_I2C_PINMUX_REG
&= CFG_I2C_PINMUX_CLR
;
335 CFG_I2C_PINMUX_REG
|= CFG_I2C_PINMUX_SET
;
338 /* enable instruction cache now */
343 * initialize higher level parts of CPU like timers
350 void uart_port_conf(void)
352 volatile gpio_t
*gpio
= (gpio_t
*)MMAP_GPIO
;
355 switch (CFG_UART_PORT
) {
357 gpio
->par_uart
|= UART0_ENABLE_MASK
;
360 gpio
->par_uart
|= UART1_ENABLE_MASK
;
363 gpio
->par_uart
|= UART2_ENABLE_MASK
;
367 #endif /* #if defined(CONFIG_M5275) */
369 #if defined(CONFIG_M5282)
371 * Breath some life into the CPU...
373 * Set up the memory map,
374 * initialize a bunch of registers,
375 * initialize the UPM's
377 void cpu_init_f(void)
379 #ifndef CONFIG_WATCHDOG
380 /* disable watchdog if we aren't using it */
384 #ifndef CONFIG_MONITOR_IS_IN_RAM
387 MCFCLOCK_SYNCR_MFD(CFG_MFD
) | MCFCLOCK_SYNCR_RFD(CFG_RFD
);
388 while (!(MCFCLOCK_SYNSR
& MCFCLOCK_SYNSR_LOCK
)) ;
390 MCFGPIO_PBCDPAR
= 0xc0;
392 /* Set up the GPIO ports */
394 MCFGPIO_PEPAR
= CFG_PEPAR
;
397 MCFGPIO_PFPAR
= CFG_PFPAR
;
400 MCFGPIO_PJPAR
= CFG_PJPAR
;
403 MCFGPIO_PSDPAR
= CFG_PSDPAR
;
406 MCFGPIO_PASPAR
= CFG_PASPAR
;
409 MCFGPIO_PEHLPAR
= CFG_PEHLPAR
;
412 MCFGPIO_PQSPAR
= CFG_PQSPAR
;
415 MCFGPIO_PTCPAR
= CFG_PTCPAR
;
418 MCFGPIO_PTDPAR
= CFG_PTDPAR
;
421 MCFGPIO_PUAPAR
= CFG_PUAPAR
;
425 MCFGPIO_DDRUA
= CFG_DDRUA
;
428 /* This is probably a bad place to setup chip selects, but everyone
431 #if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
432 defined(CFG_CS0_WIDTH) & defined(CFG_CS0_WS)
434 MCFCSM_CSAR0
= (CFG_CS0_BASE
>> 16) & 0xFFFF;
436 #if (CFG_CS0_WIDTH == 8)
437 #define CFG_CS0_PS MCFCSM_CSCR_PS_8
438 #elif (CFG_CS0_WIDTH == 16)
439 #define CFG_CS0_PS MCFCSM_CSCR_PS_16
440 #elif (CFG_CS0_WIDTH == 32)
441 #define CFG_CS0_PS MCFCSM_CSCR_PS_32
443 #error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
445 MCFCSM_CSCR0
= MCFCSM_CSCR_WS(CFG_CS0_WS
)
446 | CFG_CS0_PS
| MCFCSM_CSCR_AA
;
448 #if (CFG_CS0_RO != 0)
449 MCFCSM_CSMR0
= MCFCSM_CSMR_BAM(CFG_CS0_SIZE
- 1)
450 | MCFCSM_CSMR_WP
| MCFCSM_CSMR_V
;
452 MCFCSM_CSMR0
= MCFCSM_CSMR_BAM(CFG_CS0_SIZE
- 1) | MCFCSM_CSMR_V
;
455 #warning "Chip Select 0 are not initialized/used"
458 #if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
459 defined(CFG_CS1_WIDTH) & defined(CFG_CS1_WS)
461 MCFCSM_CSAR1
= (CFG_CS1_BASE
>> 16) & 0xFFFF;
463 #if (CFG_CS1_WIDTH == 8)
464 #define CFG_CS1_PS MCFCSM_CSCR_PS_8
465 #elif (CFG_CS1_WIDTH == 16)
466 #define CFG_CS1_PS MCFCSM_CSCR_PS_16
467 #elif (CFG_CS1_WIDTH == 32)
468 #define CFG_CS1_PS MCFCSM_CSCR_PS_32
470 #error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
472 MCFCSM_CSCR1
= MCFCSM_CSCR_WS(CFG_CS1_WS
)
473 | CFG_CS1_PS
| MCFCSM_CSCR_AA
;
475 #if (CFG_CS1_RO != 0)
476 MCFCSM_CSMR1
= MCFCSM_CSMR_BAM(CFG_CS1_SIZE
- 1)
477 | MCFCSM_CSMR_WP
| MCFCSM_CSMR_V
;
479 MCFCSM_CSMR1
= MCFCSM_CSMR_BAM(CFG_CS1_SIZE
- 1)
483 #warning "Chip Select 1 are not initialized/used"
486 #if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
487 defined(CFG_CS2_WIDTH) & defined(CFG_CS2_WS)
489 MCFCSM_CSAR2
= (CFG_CS2_BASE
>> 16) & 0xFFFF;
491 #if (CFG_CS2_WIDTH == 8)
492 #define CFG_CS2_PS MCFCSM_CSCR_PS_8
493 #elif (CFG_CS2_WIDTH == 16)
494 #define CFG_CS2_PS MCFCSM_CSCR_PS_16
495 #elif (CFG_CS2_WIDTH == 32)
496 #define CFG_CS2_PS MCFCSM_CSCR_PS_32
498 #error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
500 MCFCSM_CSCR2
= MCFCSM_CSCR_WS(CFG_CS2_WS
)
501 | CFG_CS2_PS
| MCFCSM_CSCR_AA
;
503 #if (CFG_CS2_RO != 0)
504 MCFCSM_CSMR2
= MCFCSM_CSMR_BAM(CFG_CS2_SIZE
- 1)
505 | MCFCSM_CSMR_WP
| MCFCSM_CSMR_V
;
507 MCFCSM_CSMR2
= MCFCSM_CSMR_BAM(CFG_CS2_SIZE
- 1)
511 #warning "Chip Select 2 are not initialized/used"
514 #if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
515 defined(CFG_CS3_WIDTH) & defined(CFG_CS3_WS)
517 MCFCSM_CSAR3
= (CFG_CS3_BASE
>> 16) & 0xFFFF;
519 #if (CFG_CS3_WIDTH == 8)
520 #define CFG_CS3_PS MCFCSM_CSCR_PS_8
521 #elif (CFG_CS3_WIDTH == 16)
522 #define CFG_CS3_PS MCFCSM_CSCR_PS_16
523 #elif (CFG_CS3_WIDTH == 32)
524 #define CFG_CS3_PS MCFCSM_CSCR_PS_32
526 #error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
528 MCFCSM_CSCR3
= MCFCSM_CSCR_WS(CFG_CS3_WS
)
529 | CFG_CS3_PS
| MCFCSM_CSCR_AA
;
531 #if (CFG_CS3_RO != 0)
532 MCFCSM_CSMR3
= MCFCSM_CSMR_BAM(CFG_CS3_SIZE
- 1)
533 | MCFCSM_CSMR_WP
| MCFCSM_CSMR_V
;
535 MCFCSM_CSMR3
= MCFCSM_CSMR_BAM(CFG_CS3_SIZE
- 1)
539 #warning "Chip Select 3 are not initialized/used"
542 #endif /* CONFIG_MONITOR_IS_IN_RAM */
544 /* defer enabling cache until boot (see do_go) */
545 /* icache_enable(); */
549 * initialize higher level parts of CPU like timers
556 void uart_port_conf(void)
559 switch (CFG_UART_PORT
) {
561 MCFGPIO_PUAPAR
&= 0xFc;
562 MCFGPIO_PUAPAR
|= 0x03;
565 MCFGPIO_PUAPAR
&= 0xF3;
566 MCFGPIO_PUAPAR
|= 0x0C;
569 MCFGPIO_PASPAR
&= 0xFF0F;
570 MCFGPIO_PASPAR
|= 0x00A0;
576 #if defined(CONFIG_M5249)
578 * Breath some life into the CPU...
580 * Set up the memory map,
581 * initialize a bunch of registers,
582 * initialize the UPM's
584 void cpu_init_f(void)
587 * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
588 * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
589 * which is their primary function.
592 mbar2_writeLong(MCFSIM_GPIO_FUNC
, CFG_GPIO_FUNC
);
593 mbar2_writeLong(MCFSIM_GPIO1_FUNC
, CFG_GPIO1_FUNC
);
594 mbar2_writeLong(MCFSIM_GPIO_EN
, CFG_GPIO_EN
);
595 mbar2_writeLong(MCFSIM_GPIO1_EN
, CFG_GPIO1_EN
);
596 mbar2_writeLong(MCFSIM_GPIO_OUT
, CFG_GPIO_OUT
);
597 mbar2_writeLong(MCFSIM_GPIO1_OUT
, CFG_GPIO1_OUT
);
601 * You can verify these values by using dBug's 'ird'
602 * (Internal Register Display) command
606 mbar_writeByte(MCFSIM_MPARK
, 0x30); /* 5249 Internal Core takes priority over DMA */
607 mbar_writeByte(MCFSIM_SYPCR
, 0x00);
608 mbar_writeByte(MCFSIM_SWIVR
, 0x0f);
609 mbar_writeByte(MCFSIM_SWSR
, 0x00);
610 mbar_writeLong(MCFSIM_IMR
, 0xfffffbff);
611 mbar_writeByte(MCFSIM_SWDICR
, 0x00);
612 mbar_writeByte(MCFSIM_TIMER1ICR
, 0x00);
613 mbar_writeByte(MCFSIM_TIMER2ICR
, 0x88);
614 mbar_writeByte(MCFSIM_I2CICR
, 0x00);
615 mbar_writeByte(MCFSIM_UART1ICR
, 0x00);
616 mbar_writeByte(MCFSIM_UART2ICR
, 0x00);
617 mbar_writeByte(MCFSIM_ICR6
, 0x00);
618 mbar_writeByte(MCFSIM_ICR7
, 0x00);
619 mbar_writeByte(MCFSIM_ICR8
, 0x00);
620 mbar_writeByte(MCFSIM_ICR9
, 0x00);
621 mbar_writeByte(MCFSIM_QSPIICR
, 0x00);
623 mbar2_writeLong(MCFSIM_GPIO_INT_EN
, 0x00000080);
624 mbar2_writeByte(MCFSIM_INTBASE
, 0x40); /* Base interrupts at 64 */
625 mbar2_writeByte(MCFSIM_SPURVEC
, 0x00);
626 mbar2_writeLong(MCFSIM_IDECONFIG1
, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
628 /* Setup interrupt priorities for gpio7 */
629 /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
631 /* IDE Config registers */
632 mbar2_writeLong(MCFSIM_IDECONFIG1
, 0x00000020);
633 mbar2_writeLong(MCFSIM_IDECONFIG2
, 0x00000000);
636 * Setup chip selects...
639 mbar_writeShort(MCFSIM_CSAR1
, CFG_CSAR1
);
640 mbar_writeShort(MCFSIM_CSCR1
, CFG_CSCR1
);
641 mbar_writeLong(MCFSIM_CSMR1
, CFG_CSMR1
);
643 mbar_writeShort(MCFSIM_CSAR0
, CFG_CSAR0
);
644 mbar_writeShort(MCFSIM_CSCR0
, CFG_CSCR0
);
645 mbar_writeLong(MCFSIM_CSMR0
, CFG_CSMR0
);
647 /* enable instruction cache now */
652 * initialize higher level parts of CPU like timers
659 void uart_port_conf(void)
662 switch (CFG_UART_PORT
) {
669 #endif /* #if defined(CONFIG_M5249) */