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git.ipfire.org Git - people/ms/u-boot.git/blob - cpu/mcf532x/cpu_init.c
6319658c06bb6df3f0477302a99b4756c94de399
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/m5329.h>
32 #include <asm/immap_5329.h>
35 * Breath some life into the CPU...
37 * Set up the memory map,
38 * initialize a bunch of registers,
39 * initialize the UPM's
43 volatile scm1_t
*scm1
= (scm1_t
*) MMAP_SCM1
;
44 volatile scm2_t
*scm2
= (scm2_t
*) MMAP_SCM2
;
45 volatile gpio_t
*gpio
= (gpio_t
*) MMAP_GPIO
;
46 volatile fbcs_t
*fbcs
= (fbcs_t
*) MMAP_FBCS
;
47 volatile wdog_t
*wdog
= (wdog_t
*) MMAP_WDOG
;
49 /* watchdog is enabled by default - disable the watchdog */
50 #ifndef CONFIG_WATCHDOG
54 scm1
->mpr0
= 0x77777777;
65 switch (CFG_UART_PORT
) {
67 gpio
->par_uart
= (GPIO_PAR_UART_TXD0
| GPIO_PAR_UART_RXD0
);
71 (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
74 gpio
->par_uart
= (GPIO_PAR_TIN3_URXD2
| GPIO_PAR_TIN2_UTXD2
);
78 /* Port configuration */
81 #if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
82 fbcs
->csar0
= CFG_CS0_BASE
;
83 fbcs
->cscr0
= CFG_CS0_CTRL
;
84 fbcs
->csmr0
= CFG_CS0_MASK
;
87 #if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
88 /* Latch chipselect */
89 fbcs
->csar1
= CFG_CS1_BASE
;
90 fbcs
->cscr1
= CFG_CS1_CTRL
;
91 fbcs
->csmr1
= CFG_CS1_MASK
;
94 #if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
95 fbcs
->csar2
= CFG_CS2_BASE
;
96 fbcs
->cscr2
= CFG_CS2_CTRL
;
97 fbcs
->csmr2
= CFG_CS2_MASK
;
100 #if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
101 fbcs
->csar3
= CFG_CS3_BASE
;
102 fbcs
->cscr3
= CFG_CS3_CTRL
;
103 fbcs
->csmr3
= CFG_CS3_MASK
;
106 #if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
107 fbcs
->csar4
= CFG_CS4_BASE
;
108 fbcs
->cscr4
= CFG_CS4_CTRL
;
109 fbcs
->csmr4
= CFG_CS4_MASK
;
112 #if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
113 fbcs
->csar5
= CFG_CS5_BASE
;
114 fbcs
->cscr5
= CFG_CS5_CTRL
;
115 fbcs
->csmr5
= CFG_CS5_MASK
;
120 * initialize higher level parts of CPU like timers
124 /*icache_enable(); */