cpu/mcf5445x/cpu_init.c

   1 /*
   2  *
   3  * (C) Copyright 2000-2003
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  *
   6  * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
   7  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <watchdog.h>
  30
  31 #include <asm/immap.h>
  32 #include <asm/rtc.h>
  33
  34 /*
  35  * Breath some life into the CPU...
  36  *
  37  * Set up the memory map,
  38  * initialize a bunch of registers,
  39  * initialize the UPM's
  40  */
  41 void cpu_init_f(void)
  42 {
  43         volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
  44         volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  45         volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
  46
  47         scm1->mpr = 0x77777777;
  48         scm1->pacra = 0;
  49         scm1->pacrb = 0;
  50         scm1->pacrc = 0;
  51         scm1->pacrd = 0;
  52         scm1->pacre = 0;
  53         scm1->pacrf = 0;
  54         scm1->pacrg = 0;
  55
  56         /* FlexBus */
  57         gpio->par_be =
  58             GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 |
  59             GPIO_PAR_BE_BE0_BE0;
  60         gpio->par_fbctl =
  61             GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW |
  62             GPIO_PAR_FBCTL_TS_TS;
  63
  64 #if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
  65         fbcs->csar0 = CFG_CS0_BASE;
  66         fbcs->cscr0 = CFG_CS0_CTRL;
  67         fbcs->csmr0 = CFG_CS0_MASK;
  68 #endif
  69
  70 #if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
  71         /* Latch chipselect */
  72         fbcs->csar1 = CFG_CS1_BASE;
  73         fbcs->cscr1 = CFG_CS1_CTRL;
  74         fbcs->csmr1 = CFG_CS1_MASK;
  75 #endif
  76
  77 #if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
  78         fbcs->csar2 = CFG_CS2_BASE;
  79         fbcs->cscr2 = CFG_CS2_CTRL;
  80         fbcs->csmr2 = CFG_CS2_MASK;
  81 #endif
  82
  83 #if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
  84         fbcs->csar3 = CFG_CS3_BASE;
  85         fbcs->cscr3 = CFG_CS3_CTRL;
  86         fbcs->csmr3 = CFG_CS3_MASK;
  87 #endif
  88
  89 #if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
  90         fbcs->csar4 = CFG_CS4_BASE;
  91         fbcs->cscr4 = CFG_CS4_CTRL;
  92         fbcs->csmr4 = CFG_CS4_MASK;
  93 #endif
  94
  95 #if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
  96         fbcs->csar5 = CFG_CS5_BASE;
  97         fbcs->cscr5 = CFG_CS5_CTRL;
  98         fbcs->csmr5 = CFG_CS5_MASK;
  99 #endif
 100
 101 #ifdef CONFIG_FSL_I2C
 102         gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
 103 #endif
 104
 105         icache_enable();
 106 }
 107
 108 /*
 109  * initialize higher level parts of CPU like timers
 110  */
 111 int cpu_init_r(void)
 112 {
 113 #ifdef CONFIG_MCFTMR
 114         volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
 115         volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
 116         u32 oscillator = CFG_RTC_OSCILLATOR;
 117
 118         rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF;
 119         rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF;
 120 #endif
 121
 122         return (0);
 123 }
 124
 125 void uart_port_conf(void)
 126 {
 127         volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 128
 129         /* Setup Ports: */
 130         switch (CFG_UART_PORT) {
 131         case 0:
 132                 gpio->par_uart =
 133                     (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
 134                 break;
 135         case 1:
 136                 gpio->par_uart =
 137                     (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
 138                 break;
 139         }
 140 }