cpu/microblaze/start.S

   1 /*
   2  * (C) Copyright 2007 Michal Simek
   3  * (C) Copyright 2004 Atmark Techno, Inc.
   4  *
   5  * Michal  SIMEK <monstr@monstr.eu>
   6  * Yasushi SHOJI <yashi@atmark-techno.com>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <config.h>
  28
  29         .text
  30         .global _start
  31 _start:
  32         mts     rmsr, r0        /* disable cache */
  33         addi    r1, r0, CONFIG_SYS_INIT_SP_OFFSET
  34         addi    r1, r1, -4      /* Decrement SP to top of memory */
  35         /* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
  36         addi    r6, r0, 0xb0000000      /* hex b000 opcode imm */
  37         swi     r6, r0, 0x0     /* reset address */
  38         swi     r6, r0, 0x8     /* user vector exception */
  39         swi     r6, r0, 0x10    /* interrupt */
  40         swi     r6, r0, 0x20    /* hardware exception */
  41
  42         addi    r6, r0, 0xb8080000      /* hew b808 opcode brai*/
  43         swi     r6, r0, 0x4     /* reset address */
  44         swi     r6, r0, 0xC     /* user vector exception */
  45         swi     r6, r0, 0x14    /* interrupt */
  46         swi     r6, r0, 0x24    /* hardware exception */
  47
  48 #ifdef CONFIG_SYS_RESET_ADDRESS
  49         /* reset address */
  50         addik   r6, r0, CONFIG_SYS_RESET_ADDRESS
  51         sw      r6, r1, r0
  52         lhu     r7, r1, r0
  53         shi     r7, r0, 0x2
  54         shi     r6, r0, 0x6
  55 /*
  56  * Copy U-Boot code to TEXT_BASE
  57  * solve problem with sbrk_base
  58  */
  59 #if (CONFIG_SYS_RESET_ADDRESS != TEXT_BASE)
  60         addi    r4, r0, __end
  61         addi    r5, r0, __text_start
  62         rsub    r4, r5, r4      /* size = __end - __text_start */
  63         addi    r6, r0, CONFIG_SYS_RESET_ADDRESS        /* source address */
  64         addi    r7, r0, 0       /* counter */
  65 4:
  66         lw      r8, r6, r7
  67         sw      r8, r5, r7
  68         addi    r7, r7, 0x4
  69         cmp     r8, r4, r7
  70         blti    r8, 4b
  71 #endif
  72 #endif
  73
  74 #ifdef CONFIG_SYS_USR_EXCEP
  75         /* user_vector_exception */
  76         addik   r6, r0, _exception_handler
  77         sw      r6, r1, r0
  78         lhu     r7, r1, r0
  79         shi     r7, r0, 0xa
  80         shi     r6, r0, 0xe
  81 #endif
  82
  83 #ifdef CONFIG_SYS_INTC_0
  84         /* interrupt_handler */
  85         addik   r6, r0, _interrupt_handler
  86         sw      r6, r1, r0
  87         lhu     r7, r1, r0
  88         shi     r7, r0, 0x12
  89         shi     r6, r0, 0x16
  90 #endif
  91
  92         /* hardware exception */
  93         addik   r6, r0, _hw_exception_handler
  94         sw      r6, r1, r0
  95         lhu     r7, r1, r0
  96         shi     r7, r0, 0x22
  97         shi     r6, r0, 0x26
  98
  99         /* enable instruction and data cache */
 100         mfs     r12, rmsr
 101         ori     r12, r12, 0xa0
 102         mts     rmsr, r12
 103
 104 clear_bss:
 105         /* clear BSS segments */
 106         addi    r5, r0, __bss_start
 107         addi    r4, r0, __bss_end
 108         cmp     r6, r5, r4
 109         beqi    r6, 3f
 110 2:
 111         swi     r0, r5, 0 /* write zero to loc */
 112         addi    r5, r5, 4 /* increment to next loc */
 113         cmp     r6, r5, r4 /* check if we have reach the end */
 114         bnei    r6, 2b
 115 3:      /* jumping to board_init */
 116         brai    board_init
 117 1:      bri     1b
 118
 119 /*
 120  * Read 16bit little endian
 121  */
 122         .text
 123         .global in16
 124         .ent    in16
 125         .align  2
 126 in16:   lhu     r3, r0, r5
 127         bslli   r4, r3, 8
 128         bsrli   r3, r3, 8
 129         andi    r4, r4, 0xffff
 130         or      r3, r3, r4
 131         rtsd    r15, 8
 132         sext16  r3, r3
 133         .end    in16
 134
 135 /*
 136  * Write 16bit little endian
 137  * first parameter(r5) - address, second(r6) - short value
 138  */
 139         .text
 140         .global out16
 141         .ent    out16
 142         .align  2
 143 out16:  bslli   r3, r6, 8
 144         bsrli   r6, r6, 8
 145         andi    r3, r3, 0xffff
 146         or      r3, r3, r6
 147         sh      r3, r0, r5
 148         rtsd    r15, 8
 149         or      r0, r0, r0
 150         .end    out16