cpu/mips/au1x00_eth.c

   1 /* Only eth0 supported for now
   2  *
   3  * (C) Copyright 2003
   4  * Thomas.Lange@corelatus.se
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24 #include <config.h>
  25
  26 #ifdef CONFIG_AU1X00
  27
  28 #if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
  29 #error "PHY and MII not supported yet"
  30 /* We just assume that we are running 100FD for now */
  31 /* We all use switches, right? ;-) */
  32 #endif
  33
  34 #ifdef CONFIG_AU1000
  35 /* Base address differ between cpu:s */
  36 #define ETH0_BASE AU1000_ETH0_BASE
  37 #define MAC0_ENABLE AU1000_MAC0_ENABLE
  38 #else
  39 #error "Au1100 and Au1500 not supported"
  40 #endif
  41
  42 #include <common.h>
  43 #include <malloc.h>
  44 #include <net.h>
  45 #include <command.h>
  46 #include <asm/io.h>
  47 #include <asm/au1x00.h>
  48
  49 /* Ethernet Transmit and Receive Buffers */
  50 #define DBUF_LENGTH  1520
  51 #define PKT_MAXBUF_SIZE         1518
  52
  53 static char txbuf[DBUF_LENGTH];
  54
  55 static int next_tx;
  56 static int next_rx;
  57
  58 /* 4 rx and 4 tx fifos */
  59 #define NO_OF_FIFOS 4
  60
  61 typedef struct{
  62         u32 status;
  63         u32 addr;
  64         u32 len; /* Only used for tx */
  65         u32 not_used;
  66 } mac_fifo_t;
  67
  68 mac_fifo_t mac_fifo[NO_OF_FIFOS];
  69
  70 #define MAX_WAIT 1000
  71
  72 static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
  73         volatile mac_fifo_t *fifo_tx =
  74                 (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
  75         int i;
  76         int res;
  77
  78         /* tx fifo should always be idle */
  79         fifo_tx[next_tx].len = length;
  80         fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
  81         au_sync();
  82
  83         udelay(1);
  84         i=0;
  85         while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
  86                 if(i>MAX_WAIT){
  87                         printf("TX timeout\n");
  88                         break;
  89                 }
  90                 udelay(1);
  91                 i++;
  92         }
  93
  94         /* Clear done bit */
  95         fifo_tx[next_tx].addr = 0;
  96         fifo_tx[next_tx].len = 0;
  97         au_sync();
  98
  99         res = fifo_tx[next_tx].status;
 100
 101         next_tx++;
 102         if(next_tx>=NO_OF_FIFOS){
 103                 next_tx=0;
 104         }
 105         return(res);
 106 }
 107
 108 static int au1x00_recv(struct eth_device* dev){
 109         volatile mac_fifo_t *fifo_rx =
 110                 (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
 111
 112         int length;
 113         u32 status;
 114
 115         for(;;){
 116                 if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
 117                         /* Nothing has been received */
 118                         return(-1);
 119                 }
 120
 121                 status = fifo_rx[next_rx].status;
 122
 123                 length = status&0x3FFF;
 124
 125                 if(status&RX_ERROR){
 126                         printf("Rx error 0x%x\n", status);
 127                 }
 128                 else{
 129                         /* Pass the packet up to the protocol layers. */
 130                         NetReceive(NetRxPackets[next_rx], length - 4);
 131                 }
 132
 133                 fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE;
 134
 135                 next_rx++;
 136                 if(next_rx>=NO_OF_FIFOS){
 137                         next_rx=0;
 138                 }
 139         } /* for */
 140
 141         return(0); /* Does anyone use this? */
 142 }
 143
 144 static int au1x00_init(struct eth_device* dev, bd_t * bd){
 145
 146         volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
 147         volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
 148         volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
 149         volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
 150         volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
 151         volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
 152         volatile mac_fifo_t *fifo_tx =
 153                 (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
 154         volatile mac_fifo_t *fifo_rx =
 155                 (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
 156         int i;
 157
 158         next_tx = 0;
 159         next_rx = 0;
 160
 161         /* We have to enable clocks before releasing reset */
 162         *macen = MAC_EN_CLOCK_ENABLE;
 163         udelay(10);
 164
 165         /* Enable MAC0 */
 166         /* We have to release reset before accessing registers */
 167         *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
 168                 MAC_EN_RESET1|MAC_EN_RESET2;
 169         udelay(10);
 170
 171         for(i=0;i<NO_OF_FIFOS;i++){
 172                 fifo_tx[i].len = 0;
 173                 fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
 174                 fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE;
 175         }
 176
 177         /* Put mac addr in little endian */
 178 #define ea eth_get_dev()->enetaddr
 179         *mac_addr_high  =       (ea[5] <<  8) | (ea[4]      ) ;
 180         *mac_addr_low   =       (ea[3] << 24) | (ea[2] << 16) |
 181                 (ea[1] <<  8) | (ea[0]      ) ;
 182 #undef ea
 183
 184         *mac_mcast_low = 0;
 185         *mac_mcast_high = 0;
 186
 187         *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
 188         udelay(1);
 189         *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
 190
 191         return(1);
 192 }
 193
 194 static void au1x00_halt(struct eth_device* dev){
 195 }
 196
 197 int au1x00_enet_initialize(bd_t *bis){
 198         struct eth_device* dev;
 199
 200         dev = (struct eth_device*) malloc(sizeof *dev);
 201         memset(dev, 0, sizeof *dev);
 202
 203         sprintf(dev->name, "Au1X00 ETHERNET");
 204         dev->iobase = 0;
 205         dev->priv   = 0;
 206         dev->init   = au1x00_init;
 207         dev->halt   = au1x00_halt;
 208         dev->send   = au1x00_send;
 209         dev->recv   = au1x00_recv;
 210
 211         eth_register(dev);
 212
 213         return 1;
 214 }
 215
 216 #endif /* CONFIG_AU1X00 */