2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #if defined(CONFIG_PCI) && defined(CONFIG_MPC5200)
28 #include <asm/processor.h>
33 /* System RAM mapped over PCI */
34 #define CONFIG_PCI_MEMORY_BUS CFG_SDRAM_BASE
35 #define CONFIG_PCI_MEMORY_PHYS CFG_SDRAM_BASE
36 #define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024)
38 /* PCIIWCR bit fields */
39 #define IWCR_MEM (0 << 3)
40 #define IWCR_IO (1 << 3)
41 #define IWCR_READ (0 << 1)
42 #define IWCR_READLINE (1 << 1)
43 #define IWCR_READMULT (2 << 1)
44 #define IWCR_EN (1 << 0)
46 static int mpc5200_read_config_dword(struct pci_controller
*hose
,
47 pci_dev_t dev
, int offset
, u32
* value
)
49 *(volatile u32
*)MPC5XXX_PCI_CAR
= (1 << 31) | dev
| offset
;
52 #if (defined CONFIG_PF5200 || defined CONFIG_CPCI5200)
53 if (dev
& 0x00ff0000) {
55 val
= in_le16((volatile u16
*)(CONFIG_PCI_IO_PHYS
+2));
58 val
|= in_le16((volatile u16
*)(CONFIG_PCI_IO_PHYS
+0));
61 *value
= in_le32((volatile u32
*)CONFIG_PCI_IO_PHYS
);
65 *value
= in_le32((volatile u32
*)CONFIG_PCI_IO_PHYS
);
68 *(volatile u32
*)MPC5XXX_PCI_CAR
= 0;
73 static int mpc5200_write_config_dword(struct pci_controller
*hose
,
74 pci_dev_t dev
, int offset
, u32 value
)
76 *(volatile u32
*)MPC5XXX_PCI_CAR
= (1 << 31) | dev
| offset
;
79 out_le32((volatile u32
*)CONFIG_PCI_IO_PHYS
, value
);
81 *(volatile u32
*)MPC5XXX_PCI_CAR
= 0;
86 void pci_mpc5xxx_init (struct pci_controller
*hose
)
88 hose
->first_busno
= 0;
89 hose
->last_busno
= 0xff;
92 pci_set_region(hose
->regions
+ 0,
93 CONFIG_PCI_MEMORY_BUS
,
94 CONFIG_PCI_MEMORY_PHYS
,
95 CONFIG_PCI_MEMORY_SIZE
,
96 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
98 /* PCI memory space */
99 pci_set_region(hose
->regions
+ 1,
106 pci_set_region(hose
->regions
+ 2,
112 hose
->region_count
= 3;
114 pci_register_hose(hose
);
116 /* GPIO Multiplexing - enable PCI */
117 *(vu_long
*)MPC5XXX_GPS_PORT_CONFIG
&= ~(1 << 15);
119 /* Set host bridge as pci master and enable memory decoding */
120 *(vu_long
*)MPC5XXX_PCI_CMD
|=
121 PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
;
123 /* Set maximum latency timer */
124 *(vu_long
*)MPC5XXX_PCI_CFG
|= (0xf800);
126 /* Set cache line size */
127 *(vu_long
*)MPC5XXX_PCI_CFG
= (*(vu_long
*)MPC5XXX_PCI_CFG
& ~0xff) |
128 (CFG_CACHELINE_SIZE
/ 4);
130 /* Map MBAR to PCI space */
131 *(vu_long
*)MPC5XXX_PCI_BAR0
= CFG_MBAR
;
132 *(vu_long
*)MPC5XXX_PCI_TBATR0
= CFG_MBAR
| 1;
134 /* Map RAM to PCI space */
135 *(vu_long
*)MPC5XXX_PCI_BAR1
= CONFIG_PCI_MEMORY_BUS
| (1 << 3);
136 *(vu_long
*)MPC5XXX_PCI_TBATR1
= CONFIG_PCI_MEMORY_PHYS
| 1;
138 /* Park XLB on PCI */
139 *(vu_long
*)(MPC5XXX_XLBARB
+ 0x40) &= ~((7 << 8) | (3 << 5));
140 *(vu_long
*)(MPC5XXX_XLBARB
+ 0x40) |= (3 << 8) | (3 << 5);
142 /* Disable interrupts from PCI controller */
143 *(vu_long
*)MPC5XXX_PCI_GSCR
&= ~(7 << 12);
144 *(vu_long
*)MPC5XXX_PCI_ICR
&= ~(7 << 24);
146 /* Set PCI retry counter to 0 = infinite retry. */
147 /* The default of 255 is too short for slow devices. */
148 *(vu_long
*)MPC5XXX_PCI_ICR
&= 0xFFFFFF00;
150 /* Disable initiator windows */
151 *(vu_long
*)MPC5XXX_PCI_IWCR
= 0;
153 /* Map PCI memory to physical space */
154 *(vu_long
*)MPC5XXX_PCI_IW0BTAR
= CONFIG_PCI_MEM_PHYS
|
155 (((CONFIG_PCI_MEM_SIZE
- 1) >> 8) & 0x00ff0000) |
156 (CONFIG_PCI_MEM_BUS
>> 16);
157 *(vu_long
*)MPC5XXX_PCI_IWCR
|= (IWCR_MEM
| IWCR_READ
| IWCR_EN
) << 24;
159 /* Map PCI I/O to physical space */
160 *(vu_long
*)MPC5XXX_PCI_IW1BTAR
= CONFIG_PCI_IO_PHYS
|
161 (((CONFIG_PCI_IO_SIZE
- 1) >> 8) & 0x00ff0000) |
162 (CONFIG_PCI_IO_BUS
>> 16);
163 *(vu_long
*)MPC5XXX_PCI_IWCR
|= (IWCR_IO
| IWCR_READ
| IWCR_EN
) << 16;
165 /* Reset the PCI bus */
166 *(vu_long
*)MPC5XXX_PCI_GSCR
|= 1;
168 *(vu_long
*)MPC5XXX_PCI_GSCR
&= ~1;
172 pci_hose_read_config_byte_via_dword
,
173 pci_hose_read_config_word_via_dword
,
174 mpc5200_read_config_dword
,
175 pci_hose_write_config_byte_via_dword
,
176 pci_hose_write_config_word_via_dword
,
177 mpc5200_write_config_dword
);
181 #ifdef CONFIG_PCI_SCAN_SHOW
182 printf("PCI: Bus Dev VenId DevId Class Int\n");
185 hose
->last_busno
= pci_hose_scan(hose
);
187 #endif /* CONFIG_PCI && CONFIG_MPC5200 */