cpu/mpc8220/cpu_init.c

   1 /*
   2  * (C) Copyright 2000-2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <mpc8220.h>
  26
  27 /*
  28  * Breath some life into the CPU...
  29  *
  30  * Set up the memory map,
  31  * initialize a bunch of registers.
  32  */
  33 void cpu_init_f (void)
  34 {
  35         DECLARE_GLOBAL_DATA_PTR;
  36
  37         volatile flexbus8220_t *flexbus = (volatile flexbus8220_t *) MMAP_FB;
  38         volatile pcfg8220_t *portcfg = (volatile pcfg8220_t *) MMAP_PCFG;
  39         volatile xlbarb8220_t *xlbarb = (volatile xlbarb8220_t *) MMAP_XLBARB;
  40
  41         /* Pointer is writable since we allocated a register for it */
  42         gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
  43
  44         /* Clear initial global data */
  45         memset ((void *) gd, 0, sizeof (gd_t));
  46
  47         /* Clear all port configuration */
  48         portcfg->pcfg0 = 0;
  49         portcfg->pcfg1 = 0;
  50         portcfg->pcfg2 = 0;
  51         portcfg->pcfg3 = 0;
  52
  53         /*
  54          * Flexbus Controller: configure chip selects and enable them
  55          */
  56 #if defined (CFG_CS0_BASE)
  57         flexbus->csar0 = CFG_CS0_BASE;
  58
  59 /* Sorcery-C can hang-up after CTRL reg initialization */
  60 #if defined (CFG_CS0_CTRL)
  61         flexbus->cscr0 = CFG_CS0_CTRL;
  62 #endif
  63         flexbus->csmr0 = ((CFG_CS0_MASK - 1) & 0xffff0000) | 1;
  64         __asm__ volatile ("sync");
  65 #endif
  66 #if defined (CFG_CS1_BASE)
  67         flexbus->csar1 = CFG_CS1_BASE;
  68         flexbus->cscr1 = CFG_CS1_CTRL;
  69         flexbus->csmr1 = ((CFG_CS1_MASK - 1) & 0xffff0000) | 1;
  70         __asm__ volatile ("sync");
  71 #endif
  72 #if defined (CFG_CS2_BASE)
  73         flexbus->csar2 = CFG_CS2_BASE;
  74         flexbus->cscr2 = CFG_CS2_CTRL;
  75         flexbus->csmr2 = ((CFG_CS2_MASK - 1) & 0xffff0000) | 1;
  76         portcfg->pcfg3 |= CFG_CS2_PORT3_CONFIG;
  77         __asm__ volatile ("sync");
  78 #endif
  79 #if defined (CFG_CS3_BASE)
  80         flexbus->csar3 = CFG_CS3_BASE;
  81         flexbus->cscr3 = CFG_CS3_CTRL;
  82         flexbus->csmr3 = ((CFG_CS3_MASK - 1) & 0xffff0000) | 1;
  83         portcfg->pcfg3 |= CFG_CS3_PORT3_CONFIG;
  84         __asm__ volatile ("sync");
  85 #endif
  86 #if defined (CFG_CS4_BASE)
  87         flexbus->csar4 = CFG_CS4_BASE;
  88         flexbus->cscr4 = CFG_CS4_CTRL;
  89         flexbus->csmr4 = ((CFG_CS4_MASK - 1) & 0xffff0000) | 1;
  90         portcfg->pcfg3 |= CFG_CS4_PORT3_CONFIG;
  91         __asm__ volatile ("sync");
  92 #endif
  93 #if defined (CFG_CS5_BASE)
  94         flexbus->csar5 = CFG_CS5_BASE;
  95         flexbus->cscr5 = CFG_CS5_CTRL;
  96         flexbus->csmr5 = ((CFG_CS5_MASK - 1) & 0xffff0000) | 1;
  97         portcfg->pcfg3 |= CFG_CS5_PORT3_CONFIG;
  98         __asm__ volatile ("sync");
  99 #endif
 100
 101         /* This section of the code cannot place in cpu_init_r(),
 102            it will cause the system to hang */
 103         /* enable timebase */
 104         xlbarb->addrTenTimeOut = 0x1000;
 105         xlbarb->dataTenTimeOut = 0x1000;
 106         xlbarb->busActTimeOut = 0x2000;
 107
 108         xlbarb->config = 0x00002000;
 109
 110         /* Master Priority Enable */
 111         xlbarb->mastPriority = 0;
 112         xlbarb->mastPriEn = 0x1f;
 113 }
 114
 115 /*
 116  * initialize higher level parts of CPU like time base and timers
 117  */
 118 int cpu_init_r (void)
 119 {
 120         /* this may belongs to disable interrupt section */
 121         /* mask all interrupts */
 122         *(vu_long *) 0xf0000700 = 0xfffffc00;
 123         *(vu_long *) 0xf0000714 |= 0x0001ffff;
 124         *(vu_long *) 0xf0000710 &= ~0x00000f00;
 125
 126         /* route critical ints to normal ints */
 127         *(vu_long *) 0xf0000710 |= 0x00000001;
 128
 129 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC8220_FEC)
 130         /* load FEC microcode */
 131         loadtask (0, 2);
 132 #endif
 133         return (0);
 134 }