cpu/mpc824x/cpu_init.c

   1 /*
   2  * (C) Copyright 2000
   3  * Rob Taylor. Flying Pig Systems. robt@flyingpig.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <mpc824x.h>
  27
  28 #ifndef CFG_BANK0_ROW
  29 #define CFG_BANK0_ROW 0
  30 #endif
  31 #ifndef CFG_BANK1_ROW
  32 #define CFG_BANK1_ROW 0
  33 #endif
  34 #ifndef CFG_BANK2_ROW
  35 #define CFG_BANK2_ROW 0
  36 #endif
  37 #ifndef CFG_BANK3_ROW
  38 #define CFG_BANK3_ROW 0
  39 #endif
  40 #ifndef CFG_BANK4_ROW
  41 #define CFG_BANK4_ROW 0
  42 #endif
  43 #ifndef CFG_BANK5_ROW
  44 #define CFG_BANK5_ROW 0
  45 #endif
  46 #ifndef CFG_BANK6_ROW
  47 #define CFG_BANK6_ROW 0
  48 #endif
  49 #ifndef CFG_BANK7_ROW
  50 #define CFG_BANK7_ROW 0
  51 #endif
  52 #ifndef CFG_DBUS_SIZE2
  53 #define CFG_DBUS_SIZE2 0
  54 #endif
  55
  56 /*
  57  * Breath some life into the CPU...
  58  *
  59  * Set up the memory map,
  60  * initialize a bunch of registers,
  61  */
  62 void
  63 cpu_init_f (void)
  64 {
  65 /* MOUSSE board is initialized in asm */
  66 #if !defined(CONFIG_MOUSSE) && !defined(CONFIG_BMW)
  67     register unsigned long val;
  68     CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
  69 /*    CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
  70
  71 #if defined(CONFIG_MUSENKI) || defined(CONFIG_PN62)
  72 /* Why is this here, you ask?  Try, just try setting 0x8000
  73  * in PCIACR with CONFIG_WRITE_HALFWORD()
  74  * this one was a stumper, and we are annoyed
  75  */
  76
  77 #define M_CONFIG_WRITE_HALFWORD( addr, data ) \
  78     __asm__ __volatile__(     \
  79       "                       \
  80       stw  %2,0(%0)\n         \
  81       sync\n                  \
  82       sth  %3,2(%1)\n         \
  83       sync\n                  \
  84       "                       \
  85       : /* no output */       \
  86       : "r" (CONFIG_ADDR), "r" (CONFIG_DATA),                 \
  87         "r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16))   \
  88       );
  89
  90     M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000);
  91 #endif
  92
  93     CONFIG_WRITE_BYTE(PCLSR, 0x8);      /* set PCI cache line size */
  94
  95     /*
  96      * Note that although this bit is cleared after a hard reset, it
  97      * must be explicitly set and then cleared by software during
  98      * initialization in order to guarantee correct operation of the
  99      * DLL and the SDRAM_CLK[0:3] signals (if they are used).
 100      */
 101     CONFIG_READ_BYTE (AMBOR, val);
 102     CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
 103     CONFIG_WRITE_BYTE(AMBOR, val | 0x20);
 104     CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
 105
 106     CONFIG_READ_WORD(PICR1, val);
 107 #if defined(CONFIG_MPC8240)
 108     CONFIG_WRITE_WORD( PICR1,
 109        (val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) |
 110                PIRC1_MSK | PICR1_PROC_TYPE_603E |
 111                PICR1_FLASH_WR_EN | PICR1_MCP_EN |
 112                PICR1_CF_DPARK | PICR1_EN_PCS |
 113                PICR1_CF_APARK );
 114 #elif defined(CONFIG_MPC8245)
 115     CONFIG_WRITE_WORD( PICR1,
 116        (val & (PICR1_RCS0)) |
 117                PICR1_PROC_TYPE_603E |
 118                PICR1_FLASH_WR_EN | PICR1_MCP_EN |
 119                PICR1_CF_DPARK | PICR1_NO_BUSW_CK |
 120                PICR1_DEC| PICR1_CF_APARK | 0x10);       /* 8245 UM says bit 4 must be set */
 121 #else
 122 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 123 #endif
 124
 125     CONFIG_READ_WORD(PICR2, val);
 126     val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
 127 #ifndef CONFIG_PN62
 128     val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
 129 #endif
 130     CONFIG_WRITE_WORD(PICR2, val);
 131
 132     CONFIG_WRITE_WORD(EUMBBAR, CFG_EUMB_ADDR);
 133 #ifndef CFG_RAMBOOT
 134     CONFIG_WRITE_WORD(MCCR1, (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) |
 135                                  (CFG_BANK0_ROW) |
 136                                  (CFG_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) |
 137                                  (CFG_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) |
 138                                  (CFG_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) |
 139                                  (CFG_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) |
 140                                  (CFG_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) |
 141                                  (CFG_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) |
 142                                  (CFG_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) |
 143                              (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT));
 144 #endif
 145
 146 #if defined(CFG_ASRISE) && defined(CFG_ASFALL)
 147     CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT |
 148                              CFG_ASRISE << MCCR2_ASRISE_SHIFT |
 149                              CFG_ASFALL << MCCR2_ASFALL_SHIFT);
 150 #else
 151     CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT);
 152 #endif
 153
 154 #if defined(CONFIG_MPC8240)
 155     CONFIG_WRITE_WORD(MCCR3,
 156         (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
 157         (CFG_REFREC << MCCR3_REFREC_SHIFT) |
 158         (CFG_RDLAT  << MCCR3_RDLAT_SHIFT));
 159 #elif defined(CONFIG_MPC8245)
 160     CONFIG_WRITE_WORD(MCCR3,
 161         (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
 162         (CFG_REFREC << MCCR3_REFREC_SHIFT));
 163 #else
 164 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 165 #endif
 166
 167 /* this is gross.  We think these should all be the same, and various boards
 168  *  should define CFG_ACTORW to 0 if they don't want to set it, or even, if
 169  *  its not set, we define it to zero in this file
 170  */
 171 #if defined(CONFIG_CU824) || defined(CONFIG_PN62)
 172         CONFIG_WRITE_WORD(MCCR4,
 173         (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
 174         (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
 175         MCCR4_BIT21 |
 176         (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
 177         ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
 178         (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
 179                   CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) |
 180         (CFG_ACTORW << MCCR4_ACTTORW_SHIFT) |
 181         (((CFG_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
 182 #elif defined(CONFIG_MPC8240)
 183         CONFIG_WRITE_WORD(MCCR4,
 184         (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
 185         (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
 186         MCCR4_BIT21 |
 187         (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
 188         ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
 189         (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
 190                   (CFG_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) |
 191         (((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
 192 #elif defined(CONFIG_MPC8245)
 193     CONFIG_READ_WORD(MCCR1, val);
 194     val &= MCCR1_DBUS_SIZE0;    /* test for 64-bit mem bus */
 195
 196     CONFIG_WRITE_WORD(MCCR4,
 197         (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
 198         (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
 199         (CFG_EXTROM ? MCCR4_EXTROM : 0) |
 200         (CFG_REGDIMM ? MCCR4_REGDIMM : 0) |
 201         (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
 202         ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
 203         (CFG_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
 204         (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
 205               (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT)  |
 206         (CFG_ACTORW << MCCR4_ACTTORW_SHIFT) |
 207         (((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
 208 #else
 209 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 210 #endif
 211
 212     CONFIG_WRITE_WORD(MSAR1,
 213         ( (CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
 214         (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
 215         (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
 216         (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
 217     CONFIG_WRITE_WORD(EMSAR1,
 218         ( (CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
 219         (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
 220         (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
 221         (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
 222     CONFIG_WRITE_WORD(MSAR2,
 223         ( (CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
 224         (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
 225         (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
 226         (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
 227     CONFIG_WRITE_WORD(EMSAR2,
 228         ( (CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
 229         (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
 230         (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
 231         (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
 232     CONFIG_WRITE_WORD(MEAR1,
 233         ( (CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
 234         (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
 235         (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
 236         (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
 237     CONFIG_WRITE_WORD(EMEAR1,
 238         ( (CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
 239         (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
 240         (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
 241         (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
 242     CONFIG_WRITE_WORD(MEAR2,
 243         ( (CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
 244         (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
 245         (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
 246         (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
 247     CONFIG_WRITE_WORD(EMEAR2,
 248         ( (CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
 249         (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
 250         (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
 251         (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
 252
 253     CONFIG_WRITE_BYTE(ODCR, CFG_ODCR);
 254 #ifdef CFG_DLL_MAX_DELAY
 255         CONFIG_WRITE_BYTE(MIOCR1, CFG_DLL_MAX_DELAY);   /* needed to make DLL lock */
 256 #endif
 257 #if defined(CFG_DLL_EXTEND) && defined(CFG_PCI_HOLD_DEL)
 258         CONFIG_WRITE_BYTE(PMCR2, CFG_DLL_EXTEND | CFG_PCI_HOLD_DEL);
 259 #endif
 260 #if defined(MIOCR2) && defined(CFG_SDRAM_DSCD)
 261         CONFIG_WRITE_BYTE(MIOCR2, CFG_SDRAM_DSCD);      /* change memory input */
 262 #endif /* setup & hold time */
 263
 264     CONFIG_WRITE_BYTE(MBER,
 265          CFG_BANK0_ENABLE |
 266         (CFG_BANK1_ENABLE << 1) |
 267         (CFG_BANK2_ENABLE << 2) |
 268         (CFG_BANK3_ENABLE << 3) |
 269         (CFG_BANK4_ENABLE << 4) |
 270         (CFG_BANK5_ENABLE << 5) |
 271         (CFG_BANK6_ENABLE << 6) |
 272         (CFG_BANK7_ENABLE << 7));
 273
 274 #ifdef CFG_PGMAX
 275     CONFIG_WRITE_BYTE(MPMR, CFG_PGMAX);
 276 #endif
 277
 278     /* ! Wait 200us before initialize other registers */
 279     /*FIXME: write a decent udelay wait */
 280     __asm__ __volatile__(
 281       " mtctr   %0 \n \
 282        0: bdnz   0b\n"
 283       :
 284       : "r" (0x10000));
 285
 286    CONFIG_READ_WORD(MCCR1, val);
 287    CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
 288    __asm__ __volatile__("eieio");
 289
 290 #endif /* !CONFIG_MOUSSE && !CONFIG_BMW */
 291 }
 292
 293
 294 #ifdef CONFIG_MOUSSE
 295 #ifdef INCLUDE_MPC107_REPORT
 296 struct MPC107_s{
 297     unsigned int iobase;
 298     char desc[120];
 299 } MPC107Regs[] ={
 300     {BMC_BASE+0x0,  "MPC107 Vendor/Device ID"},
 301     {BMC_BASE+0x4,  "MPC107 PCI Command/Status Register"},
 302     {BMC_BASE+0x8,  "MPC107 Revision"},
 303     {BMC_BASE+0xC,  "MPC107 Cache Line Size"},
 304     {BMC_BASE+0x10, "MPC107 LMBAR"},
 305     {BMC_BASE+0x14, "MPC824x PCSR"},
 306     {BMC_BASE+0xA8, "MPC824x PICR1"},
 307     {BMC_BASE+0xAC, "MPC824x PICR2"},
 308     {BMC_BASE+0x46, "MPC824x PACR"},
 309     {BMC_BASE+0x310, "MPC824x ITWR"},
 310     {BMC_BASE+0x300, "MPC824x OMBAR"},
 311     {BMC_BASE+0x308, "MPC824x OTWR"},
 312     {BMC_BASE+0x14, "MPC107 Peripheral Control and Status Register"},
 313     {BMC_BASE+0x78, "MPC107 EUMBAR"},
 314     {BMC_BASE+0xC0, "MPC107 Processor Bus Error Status"},
 315     {BMC_BASE+0xC4, "MPC107 PCI Bus Error Status"},
 316     {BMC_BASE+0xC8, "MPC107 Processor/PCI Error Address"},
 317     {BMC_BASE+0xE0, "MPC107 AMBOR Register"},
 318     {BMC_BASE+0xF0, "MPC107 MCCR1 Register"},
 319     {BMC_BASE+0xF4, "MPC107 MCCR2 Register"},
 320     {BMC_BASE+0xF8, "MPC107 MCCR3 Register"},
 321     {BMC_BASE+0xFC, "MPC107 MCCR4 Register"}
 322 };
 323 #define N_MPC107_Regs   (sizeof(MPC107Regs)/sizeof(MPC107Regs[0]))
 324 #endif /* INCLUDE_MPC107_REPORT */
 325 #endif /* CONFIG_MOUSSE */
 326
 327 /*
 328  * initialize higher level parts of CPU like time base and timers
 329  */
 330 int cpu_init_r (void)
 331 {
 332 #ifdef CONFIG_MOUSSE
 333 #ifdef INCLUDE_MPC107_REPORT
 334         unsigned int tmp = 0, i;
 335 #endif
 336         /*
 337          * Initialize the EUMBBAR (Embedded Util Mem Block Base Addr Reg).
 338          * This is necessary before the EPIC, DMA ctlr, I2C ctlr, etc. can
 339          * be accessed.
 340          */
 341
 342 #ifdef CONFIG_MPC8240                   /* only on MPC8240 */
 343         mpc824x_mpc107_setreg (EUMBBAR, EUMBBAR_VAL);
 344         /* MOT/SPS: Issue #10002, PCI (FD Alias enable) */
 345         mpc824x_mpc107_setreg (AMBOR, 0x000000C0);
 346 #endif
 347
 348
 349 #ifdef INCLUDE_MPC107_REPORT
 350         /* Check MPC824x PCI Device and Vendor ID */
 351         while ((tmp = mpc824x_mpc107_getreg (BMC_BASE)) != 0x31057) {
 352                 printf ("       MPC107: offset=0x%x, val = 0x%x\n",
 353                         BMC_BASE,
 354                         tmp);
 355         }
 356
 357         for (i = 0; i < N_MPC107_Regs; i++) {
 358                 printf ("       0x%x/%s = 0x%x\n",
 359                         MPC107Regs[i].iobase,
 360                         MPC107Regs[i].desc,
 361                         mpc824x_mpc107_getreg (MPC107Regs[i].iobase));
 362         }
 363
 364         printf ("IBAT0L = 0x%08X\n", mfspr (IBAT0L));
 365         printf ("IBAT0U = 0x%08X\n", mfspr (IBAT0U));
 366         printf ("IBAT1L = 0x%08X\n", mfspr (IBAT1L));
 367         printf ("IBAT1U = 0x%08X\n", mfspr (IBAT1U));
 368         printf ("IBAT2L = 0x%08X\n", mfspr (IBAT2L));
 369         printf ("IBAT2U = 0x%08X\n", mfspr (IBAT2U));
 370         printf ("IBAT3L = 0x%08X\n", mfspr (IBAT3L));
 371         printf ("IBAT3U = 0x%08X\n", mfspr (IBAT3U));
 372         printf ("DBAT0L = 0x%08X\n", mfspr (DBAT0L));
 373         printf ("DBAT0U = 0x%08X\n", mfspr (DBAT0U));
 374         printf ("DBAT1L = 0x%08X\n", mfspr (DBAT1L));
 375         printf ("DBAT1U = 0x%08X\n", mfspr (DBAT1U));
 376         printf ("DBAT2L = 0x%08X\n", mfspr (DBAT2L));
 377         printf ("DBAT2U = 0x%08X\n", mfspr (DBAT2U));
 378         printf ("DBAT3L = 0x%08X\n", mfspr (DBAT3L));
 379         printf ("DBAT3U = 0x%08X\n", mfspr (DBAT3U));
 380 #endif /* INCLUDE_MPC107_REPORT */
 381 #endif /* CONFIG_MOUSSE */
 382         return (0);
 383 }