cpu/mpc824x/drivers/dma/README

   1 CONTENT:
   2
   3    dma.h
   4    dma1.c
   5    dma2.s
   6
   7 WHAT ARE THESE FILES:
   8
   9 These files contain MPC8240 (Kahlua) DMA controller
  10 driver routines. The driver routines are not
  11 written for any specific operating system.
  12 They serves the purpose of code sample, and
  13 jump-start for using the MPC8240 DMA controller.
  14
  15 For the reason of correctness of C language
  16 syntax, these files are compiled by Metaware
  17 C compiler and assembler.
  18
  19 ENDIAN NOTATION:
  20
  21 The algorithm is designed for big-endian mode,
  22 software is responsible for byte swapping.
  23
  24 USAGE:
  25
  26 1. The host system that is running on MPC8240
  27    or using MPC8240 as I/O device shall link
  28    the files listed here. The memory location
  29    of driver routines shall take into account of
  30    that driver routines need to run in supervisor
  31    mode and they process DMA controller interrupt.
  32
  33 2. The host system is responsible for configuring
  34    the MPC8240 including Embedded Utilities Memory
  35    Block. Since the DMA controller on MPC8240 can
  36    be accessed by either local 603e core or the host
  37    that MPC8240 serves as I/O processor through host
  38    PCI configuration, it is important that the local
  39    processor uses EUMBBAR to access its local DMA
  40    controller while the PCI master uses I/O
  41    processor's PCSRBAR to access the DMA controller
  42    on I/O device.
  43
  44    To qualify whether is EUMBBAR or PCSRBAR, one
  45    additional parameter is requied from the host
  46    system, LOCAL or REMOTE so that the base value
  47    can be correctly interpreted.
  48
  49 3. If the host system is also using the EPIC unit
  50    on MPC8240, the system can register the
  51    DMA_ISR with the EPIC including other
  52    desired resources.
  53
  54    If the host system does not using the EPIC unit
  55    on MPC8240, DMA_ISR function can be called for
  56    each desired time interval.
  57
  58    In both cases, the host system is free to
  59    provide its own interrupt service routine.
  60
  61 4. To start a direct mode DMA transaction,
  62    use DMA_Bld_Curr with the start parameter
  63    set to 1.
  64
  65    To start a chaining mode DMA transaction,
  66    the application shall build descriptors
  67    in memory first, next, use DMA_Bld_Desp
  68    with the start parameter set to 1.
  69
  70 5. DMA_Start function clears, then sets the CS
  71    bit of DMA mode register.
  72
  73    DMA_Halt function clears the CS bit of DMA
  74    mode register.
  75
  76    These functions can be used to start and
  77    halt the DMA transaction.
  78
  79    If the chaining descriptors has been
  80    modified since the last time a DMA
  81    transaction started, use DMA_Chn_Cnt
  82    function to let DMA controller process
  83    the modified descriptor chain without
  84    stopping or disturbing the current DMA
  85    transaction.
  86
  87    It is the host system's responsibility of
  88    setting up the correct DMA transfer mode
  89    and pass the correct memory address parameters.
  90
  91 6. It is the host system's responsibility of
  92    queueing the DMA I/O request. The host
  93    system can call the DMA_ISR with its own
  94    desired interrupt service subroutines to
  95    handle each individual interrupt and queued
  96    DMA I/O requests.
  97
  98 7. The DMA driver routines contains a set
  99    of utilities, Set and Get, for host system
 100    to query and modify the desired DMA registers.