cpu/mpc8260/cpu.c

   1 /*
   2  * (C) Copyright 2000-2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x
  26  *
  27  * written or collected and sometimes rewritten by
  28  * Magnus Damm <damm@bitsmart.com>
  29  *
  30  * modified by
  31  * Wolfgang Denk <wd@denx.de>
  32  *
  33  * modified for 8260 by
  34  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
  35  *
  36  * added 8260 masks by
  37  * Marius Groeger <mag@sysgo.de>
  38  *
  39  * added HiP7 (8270/8275/8280) processors support by
  40  * Yuli Barcohen <yuli@arabellasw.com>
  41  */
  42
  43 #include <common.h>
  44 #include <watchdog.h>
  45 #include <command.h>
  46 #include <mpc8260.h>
  47 #include <asm/processor.h>
  48 #include <asm/cpm_8260.h>
  49
  50 int checkcpu (void)
  51 {
  52         DECLARE_GLOBAL_DATA_PTR;
  53
  54         volatile immap_t *immap = (immap_t *) CFG_IMMR;
  55         ulong clock = gd->cpu_clk;
  56         uint pvr = get_pvr ();
  57         uint immr, rev, m, k;
  58         char buf[32];
  59
  60         puts ("CPU:   ");
  61
  62         switch (pvr) {
  63         case PVR_8260:
  64         case PVR_8260_HIP3:
  65                 k = 3;
  66                 break;
  67         case PVR_8260_HIP4:
  68                 k = 4;
  69                 break;
  70         case PVR_8260_HIP7R1:
  71         case PVR_8260_HIP7:
  72                 k = 7;
  73                 break;
  74         default:
  75                 return -1;      /* whoops! not an MPC8260 */
  76         }
  77         rev = pvr & 0xff;
  78
  79         immr = immap->im_memctl.memc_immr;
  80         if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
  81                 return -1;      /* whoops! someone moved the IMMR */
  82
  83         printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
  84
  85         /*
  86          * the bottom 16 bits of the immr are the Part Number and Mask Number
  87          * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the
  88          * RISC Microcode Revision Number (13-10).
  89          * For the 8260, Motorola doesn't include the Microcode Revision
  90          * in the mask.
  91          */
  92         m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK);
  93         k = *((ushort *) & immap->im_dprambase[PROFF_REVNUM]);
  94
  95         switch (m) {
  96         case 0x0000:
  97                 puts ("0.2 2J24M");
  98                 break;
  99         case 0x0010:
 100                 puts ("A.0 K22A");
 101                 break;
 102         case 0x0011:
 103                 puts ("A.1 1K22A-XC");
 104                 break;
 105         case 0x0001:
 106                 puts ("B.1 1K23A");
 107                 break;
 108         case 0x0021:
 109                 puts ("B.2 2K23A-XC");
 110                 break;
 111         case 0x0023:
 112                 puts ("B.3 3K23A");
 113                 break;
 114         case 0x0024:
 115                 puts ("C.2 6K23A");
 116                 break;
 117         case 0x0060:
 118                 puts ("A.0(A) 2K25A");
 119                 break;
 120         case 0x0062:
 121                 puts ("B.1 4K25A");
 122                 break;
 123         case 0x0064:
 124                 puts ("C.0 5K25A");
 125                 break;
 126         case 0x0A00:
 127                 puts ("0.0 0K49M");
 128                 break;
 129         case 0x0A01:
 130                 puts ("0.1 1K49M");
 131                 break;
 132         default:
 133                 printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
 134                 break;
 135         }
 136
 137         printf (") at %s MHz\n", strmhz (buf, clock));
 138
 139         return 0;
 140 }
 141
 142 /* ------------------------------------------------------------------------- */
 143 /* configures a UPM by writing into the UPM RAM array                        */
 144 /* uses bank 11 and a dummy physical address (=BRx_BA_MSK)                   */
 145 /* NOTE: the physical address chosen must not overlap into any other area    */
 146 /* mapped by the memory controller because bank 11 has the lowest priority   */
 147
 148 void upmconfig (uint upm, uint * table, uint size)
 149 {
 150         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 151         volatile memctl8260_t *memctl = &immap->im_memctl;
 152         volatile uchar *dummy = (uchar *) BRx_BA_MSK;   /* set all BA bits */
 153         uint i;
 154
 155         /* first set up bank 11 to reference the correct UPM at a dummy address */
 156
 157         memctl->memc_or11 = ORxU_AM_MSK;        /* set all AM bits */
 158
 159         switch (upm) {
 160
 161         case UPMA:
 162                 memctl->memc_br11 =
 163                         ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA |
 164                         BRx_V;
 165                 memctl->memc_mamr = MxMR_OP_WARR;
 166                 break;
 167
 168         case UPMB:
 169                 memctl->memc_br11 =
 170                         ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB |
 171                         BRx_V;
 172                 memctl->memc_mbmr = MxMR_OP_WARR;
 173                 break;
 174
 175         case UPMC:
 176                 memctl->memc_br11 =
 177                         ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC |
 178                         BRx_V;
 179                 memctl->memc_mcmr = MxMR_OP_WARR;
 180                 break;
 181
 182         default:
 183                 panic ("upmconfig passed invalid UPM number (%u)\n", upm);
 184                 break;
 185
 186         }
 187
 188         /*
 189          * at this point, the dummy address is set up to access the selected UPM,
 190          * the MAD pointer is zero, and the MxMR OP is set for writing to RAM
 191          *
 192          * now we simply load the mdr with each word and poke the dummy address.
 193          * the MAD is incremented on each access.
 194          */
 195
 196         for (i = 0; i < size; i++) {
 197                 memctl->memc_mdr = table[i];
 198                 *dummy = 0;
 199         }
 200
 201         /* now kill bank 11 */
 202         memctl->memc_br11 = 0;
 203 }
 204
 205 /* ------------------------------------------------------------------------- */
 206
 207 int
 208 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 209 {
 210         ulong msr, addr;
 211
 212         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 213
 214         immap->im_clkrst.car_rmr = RMR_CSRE;    /* Checkstop Reset enable */
 215
 216         /* Interrupts and MMU off */
 217         __asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
 218
 219         msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
 220         __asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
 221
 222         /*
 223          * Trying to execute the next instruction at a non-existing address
 224          * should cause a machine check, resulting in reset
 225          */
 226 #ifdef CFG_RESET_ADDRESS
 227         addr = CFG_RESET_ADDRESS;
 228 #else
 229         /*
 230          * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
 231          * - sizeof (ulong) is usually a valid address. Better pick an address
 232          * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
 233          */
 234         addr = CFG_MONITOR_BASE - sizeof (ulong);
 235 #endif
 236         ((void (*)(void)) addr) ();
 237         return 1;
 238
 239 }
 240
 241 /* ------------------------------------------------------------------------- */
 242
 243 /*
 244  * Get timebase clock frequency (like cpu_clk in Hz)
 245  *
 246  */
 247 unsigned long get_tbclk (void)
 248 {
 249         DECLARE_GLOBAL_DATA_PTR;
 250
 251         ulong tbclk;
 252
 253         tbclk = (gd->bus_clk + 3L) / 4L;
 254
 255         return (tbclk);
 256 }
 257
 258 /* ------------------------------------------------------------------------- */
 259
 260 #if defined(CONFIG_WATCHDOG)
 261 void watchdog_reset (void)
 262 {
 263         int re_enable = disable_interrupts ();
 264
 265         reset_8260_watchdog ((immap_t *) CFG_IMMR);
 266         if (re_enable)
 267                 enable_interrupts ();
 268 }
 269 #endif /* CONFIG_WATCHDOG */
 270
 271 /* ------------------------------------------------------------------------- */