cpu/mpc8260/cpu.c

   1 /*
   2  * (C) Copyright 2000-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x
  26  *
  27  * written or collected and sometimes rewritten by
  28  * Magnus Damm <damm@bitsmart.com>
  29  *
  30  * modified by
  31  * Wolfgang Denk <wd@denx.de>
  32  *
  33  * modified for 8260 by
  34  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
  35  *
  36  * added 8260 masks by
  37  * Marius Groeger <mag@sysgo.de>
  38  *
  39  * added HiP7 (824x/827x/8280) processors support by
  40  * Yuli Barcohen <yuli@arabellasw.com>
  41  */
  42
  43 #include <common.h>
  44 #include <watchdog.h>
  45 #include <command.h>
  46 #include <mpc8260.h>
  47 #include <asm/processor.h>
  48 #include <asm/cpm_8260.h>
  49
  50 DECLARE_GLOBAL_DATA_PTR;
  51
  52 int checkcpu (void)
  53 {
  54         volatile immap_t *immap = (immap_t *) CFG_IMMR;
  55         ulong clock = gd->cpu_clk;
  56         uint pvr = get_pvr ();
  57         uint immr, rev, m, k;
  58         char buf[32];
  59
  60         puts ("CPU:   ");
  61
  62         switch (pvr) {
  63         case PVR_8260:
  64         case PVR_8260_HIP3:
  65                 k = 3;
  66                 break;
  67         case PVR_8260_HIP4:
  68                 k = 4;
  69                 break;
  70         case PVR_8260_HIP7R1:
  71         case PVR_8260_HIP7RA:
  72         case PVR_8260_HIP7:
  73                 k = 7;
  74                 break;
  75         default:
  76                 return -1;      /* whoops! not an MPC8260 */
  77         }
  78         rev = pvr & 0xff;
  79
  80         immr = immap->im_memctl.memc_immr;
  81         if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
  82                 return -1;      /* whoops! someone moved the IMMR */
  83
  84         printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
  85
  86         /*
  87          * the bottom 16 bits of the immr are the Part Number and Mask Number
  88          * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the
  89          * RISC Microcode Revision Number (13-10).
  90          * For the 8260, Motorola doesn't include the Microcode Revision
  91          * in the mask.
  92          */
  93         m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK);
  94         k = *((ushort *) & immap->im_dprambase[PROFF_REVNUM]);
  95
  96         switch (m) {
  97         case 0x0000:
  98                 puts ("0.2 2J24M");
  99                 break;
 100         case 0x0010:
 101                 puts ("A.0 K22A");
 102                 break;
 103         case 0x0011:
 104                 puts ("A.1 1K22A-XC");
 105                 break;
 106         case 0x0001:
 107                 puts ("B.1 1K23A");
 108                 break;
 109         case 0x0021:
 110                 puts ("B.2 2K23A-XC");
 111                 break;
 112         case 0x0023:
 113                 puts ("B.3 3K23A");
 114                 break;
 115         case 0x0024:
 116                 puts ("C.2 6K23A");
 117                 break;
 118         case 0x0060:
 119                 puts ("A.0(A) 2K25A");
 120                 break;
 121         case 0x0062:
 122                 puts ("B.1 4K25A");
 123                 break;
 124         case 0x0064:
 125                 puts ("C.0 5K25A");
 126                 break;
 127         case 0x0A00:
 128                 puts ("0.0 0K49M");
 129                 break;
 130         case 0x0A01:
 131                 puts ("0.1 1K49M");
 132                 break;
 133         case 0x0A10:
 134                 puts ("1.0 1K49M");
 135                 break;
 136         case 0x0C00:
 137                 puts ("0.0 0K50M");
 138                 break;
 139         case 0x0C10:
 140                 puts ("1.0 1K50M");
 141                 break;
 142         case 0x0D00:
 143                 puts ("0.0 0K50M");
 144                 break;
 145         case 0x0D10:
 146                 puts ("1.0 1K50M");
 147                 break;
 148         default:
 149                 printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
 150                 break;
 151         }
 152
 153         printf (") at %s MHz\n", strmhz (buf, clock));
 154
 155         return 0;
 156 }
 157
 158 /* ------------------------------------------------------------------------- */
 159 /* configures a UPM by writing into the UPM RAM array                        */
 160 /* uses bank 11 and a dummy physical address (=BRx_BA_MSK)                   */
 161 /* NOTE: the physical address chosen must not overlap into any other area    */
 162 /* mapped by the memory controller because bank 11 has the lowest priority   */
 163
 164 void upmconfig (uint upm, uint * table, uint size)
 165 {
 166         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 167         volatile memctl8260_t *memctl = &immap->im_memctl;
 168         volatile uchar *dummy = (uchar *) BRx_BA_MSK;   /* set all BA bits */
 169         uint i;
 170
 171         /* first set up bank 11 to reference the correct UPM at a dummy address */
 172
 173         memctl->memc_or11 = ORxU_AM_MSK;        /* set all AM bits */
 174
 175         switch (upm) {
 176
 177         case UPMA:
 178                 memctl->memc_br11 =
 179                         ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA |
 180                         BRx_V;
 181                 memctl->memc_mamr = MxMR_OP_WARR;
 182                 break;
 183
 184         case UPMB:
 185                 memctl->memc_br11 =
 186                         ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB |
 187                         BRx_V;
 188                 memctl->memc_mbmr = MxMR_OP_WARR;
 189                 break;
 190
 191         case UPMC:
 192                 memctl->memc_br11 =
 193                         ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC |
 194                         BRx_V;
 195                 memctl->memc_mcmr = MxMR_OP_WARR;
 196                 break;
 197
 198         default:
 199                 panic ("upmconfig passed invalid UPM number (%u)\n", upm);
 200                 break;
 201
 202         }
 203
 204         /*
 205          * at this point, the dummy address is set up to access the selected UPM,
 206          * the MAD pointer is zero, and the MxMR OP is set for writing to RAM
 207          *
 208          * now we simply load the mdr with each word and poke the dummy address.
 209          * the MAD is incremented on each access.
 210          */
 211
 212         for (i = 0; i < size; i++) {
 213                 memctl->memc_mdr = table[i];
 214                 *dummy = 0;
 215         }
 216
 217         /* now kill bank 11 */
 218         memctl->memc_br11 = 0;
 219 }
 220
 221 /* ------------------------------------------------------------------------- */
 222
 223 #if !defined(CONFIG_HAVE_OWN_RESET)
 224 int
 225 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 226 {
 227         ulong msr, addr;
 228
 229         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 230
 231         immap->im_clkrst.car_rmr = RMR_CSRE;    /* Checkstop Reset enable */
 232
 233         /* Interrupts and MMU off */
 234         __asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
 235
 236         msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
 237         __asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
 238
 239         /*
 240          * Trying to execute the next instruction at a non-existing address
 241          * should cause a machine check, resulting in reset
 242          */
 243 #ifdef CFG_RESET_ADDRESS
 244         addr = CFG_RESET_ADDRESS;
 245 #else
 246         /*
 247          * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
 248          * - sizeof (ulong) is usually a valid address. Better pick an address
 249          * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
 250          */
 251         addr = CFG_MONITOR_BASE - sizeof (ulong);
 252 #endif
 253         ((void (*)(void)) addr) ();
 254         return 1;
 255
 256 }
 257 #endif  /* CONFIG_HAVE_OWN_RESET */
 258
 259 /* ------------------------------------------------------------------------- */
 260
 261 /*
 262  * Get timebase clock frequency (like cpu_clk in Hz)
 263  *
 264  */
 265 unsigned long get_tbclk (void)
 266 {
 267         ulong tbclk;
 268
 269         tbclk = (gd->bus_clk + 3L) / 4L;
 270
 271         return (tbclk);
 272 }
 273
 274 /* ------------------------------------------------------------------------- */
 275
 276 #if defined(CONFIG_WATCHDOG)
 277 void watchdog_reset (void)
 278 {
 279         int re_enable = disable_interrupts ();
 280
 281         reset_8260_watchdog ((immap_t *) CFG_IMMR);
 282         if (re_enable)
 283                 enable_interrupts ();
 284 }
 285 #endif /* CONFIG_WATCHDOG */
 286
 287 /* ------------------------------------------------------------------------- */