cpu/mpc83xx/cpu.c

   1 /*
   2  * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * CPU specific code for the MPC83xx family.
  25  *
  26  * Derived from the MPC8260 and MPC85xx.
  27  */
  28
  29 #include <common.h>
  30 #include <watchdog.h>
  31 #include <command.h>
  32 #include <mpc83xx.h>
  33 #include <asm/processor.h>
  34 #if defined(CONFIG_OF_FLAT_TREE)
  35 #include <ft_build.h>
  36 #elif defined(CONFIG_OF_LIBFDT)
  37 #include <libfdt.h>
  38 #endif
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 int checkcpu(void)
  43 {
  44         volatile immap_t *immr;
  45         ulong clock = gd->cpu_clk;
  46         u32 pvr = get_pvr();
  47         u32 spridr;
  48         char buf[32];
  49
  50         immr = (immap_t *)CFG_IMMR;
  51
  52         puts("CPU:   ");
  53
  54         switch (pvr & 0xffff0000) {
  55                 case PVR_E300C1:
  56                         printf("e300c1, ");
  57                         break;
  58
  59                 case PVR_E300C2:
  60                         printf("e300c2, ");
  61                         break;
  62
  63                 case PVR_E300C3:
  64                         printf("e300c3, ");
  65                         break;
  66
  67                 default:
  68                         printf("Unknown core, ");
  69         }
  70
  71         spridr = immr->sysconf.spridr;
  72         switch(spridr) {
  73         case SPR_8349E_REV10:
  74         case SPR_8349E_REV11:
  75         case SPR_8349E_REV31:
  76                 puts("MPC8349E, ");
  77                 break;
  78         case SPR_8349_REV10:
  79         case SPR_8349_REV11:
  80         case SPR_8349_REV31:
  81                 puts("MPC8349, ");
  82                 break;
  83         case SPR_8347E_REV10_TBGA:
  84         case SPR_8347E_REV11_TBGA:
  85         case SPR_8347E_REV31_TBGA:
  86         case SPR_8347E_REV10_PBGA:
  87         case SPR_8347E_REV11_PBGA:
  88         case SPR_8347E_REV31_PBGA:
  89                 puts("MPC8347E, ");
  90                 break;
  91         case SPR_8347_REV10_TBGA:
  92         case SPR_8347_REV11_TBGA:
  93         case SPR_8347_REV31_TBGA:
  94         case SPR_8347_REV10_PBGA:
  95         case SPR_8347_REV11_PBGA:
  96         case SPR_8347_REV31_PBGA:
  97                 puts("MPC8347, ");
  98                 break;
  99         case SPR_8343E_REV10:
 100         case SPR_8343E_REV11:
 101         case SPR_8343E_REV31:
 102                 puts("MPC8343E, ");
 103                 break;
 104         case SPR_8343_REV10:
 105         case SPR_8343_REV11:
 106         case SPR_8343_REV31:
 107                 puts("MPC8343, ");
 108                 break;
 109         case SPR_8360E_REV10:
 110         case SPR_8360E_REV11:
 111         case SPR_8360E_REV12:
 112         case SPR_8360E_REV20:
 113         case SPR_8360E_REV21:
 114                 puts("MPC8360E, ");
 115                 break;
 116         case SPR_8360_REV10:
 117         case SPR_8360_REV11:
 118         case SPR_8360_REV12:
 119         case SPR_8360_REV20:
 120         case SPR_8360_REV21:
 121                 puts("MPC8360, ");
 122                 break;
 123         case SPR_8323E_REV10:
 124         case SPR_8323E_REV11:
 125                 puts("MPC8323E, ");
 126                 break;
 127         case SPR_8323_REV10:
 128         case SPR_8323_REV11:
 129                 puts("MPC8323, ");
 130                 break;
 131         case SPR_8321E_REV10:
 132         case SPR_8321E_REV11:
 133                 puts("MPC8321E, ");
 134                 break;
 135         case SPR_8321_REV10:
 136         case SPR_8321_REV11:
 137                 puts("MPC8321, ");
 138                 break;
 139         case SPR_8311_REV10:
 140                 puts("MPC8311, ");
 141                 break;
 142         case SPR_8311E_REV10:
 143                 puts("MPC8311E, ");
 144                 break;
 145         case SPR_8313_REV10:
 146                 puts("MPC8313, ");
 147                 break;
 148         case SPR_8313E_REV10:
 149                 puts("MPC8313E, ");
 150                 break;
 151         default:
 152                 printf("Rev: Unknown revision number:%08x\n"
 153                         "Warning: Unsupported cpu revision!\n",spridr);
 154                 return 0;
 155         }
 156
 157 #if defined(CONFIG_MPC834X)
 158         /* Multiple revisons of 834x processors may have the same SPRIDR value.
 159          * So use PVR to identify the revision number.
 160          */
 161         printf("Rev: %02x at %s MHz", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
 162 #else
 163         printf("Rev: %02x at %s MHz", spridr & 0x0000FFFF, strmhz(buf, clock));
 164 #endif
 165         printf(", CSB: %4d MHz\n", gd->csb_clk / 1000000);
 166
 167         return 0;
 168 }
 169
 170
 171 /*
 172  * Program a UPM with the code supplied in the table.
 173  *
 174  * The 'dummy' variable is used to increment the MAD. 'dummy' is
 175  * supposed to be a pointer to the memory of the device being
 176  * programmed by the UPM.  The data in the MDR is written into
 177  * memory and the MAD is incremented every time there's a read
 178  * from 'dummy'. Unfortunately, the current prototype for this
 179  * function doesn't allow for passing the address of this
 180  * device, and changing the prototype will break a number lots
 181  * of other code, so we need to use a round-about way of finding
 182  * the value for 'dummy'.
 183  *
 184  * The value can be extracted from the base address bits of the
 185  * Base Register (BR) associated with the specific UPM.  To find
 186  * that BR, we need to scan all 8 BRs until we find the one that
 187  * has its MSEL bits matching the UPM we want.  Once we know the
 188  * right BR, we can extract the base address bits from it.
 189  *
 190  * The MxMR and the BR and OR of the chosen bank should all be
 191  * configured before calling this function.
 192  *
 193  * Parameters:
 194  * upm: 0=UPMA, 1=UPMB, 2=UPMC
 195  * table: Pointer to an array of values to program
 196  * size: Number of elements in the array.  Must be 64 or less.
 197  */
 198 void upmconfig (uint upm, uint *table, uint size)
 199 {
 200 #if defined(CONFIG_MPC834X)
 201         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 202         volatile lbus83xx_t *lbus = &immap->lbus;
 203         volatile uchar *dummy = NULL;
 204         const u32 msel = (upm + 4) << BR_MSEL_SHIFT;    /* What the MSEL field in BRn should be */
 205         volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
 206         uint i;
 207
 208         /* Scan all the banks to determine the base address of the device */
 209         for (i = 0; i < 8; i++) {
 210                 if ((lbus->bank[i].br & BR_MSEL) == msel) {
 211                         dummy = (uchar *) (lbus->bank[i].br & BR_BA);
 212                         break;
 213                 }
 214         }
 215
 216         if (!dummy) {
 217                 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
 218                 hang();
 219         }
 220
 221         /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
 222         *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
 223
 224         for (i = 0; i < size; i++) {
 225                 lbus->mdr = table[i];
 226                 __asm__ __volatile__ ("sync");
 227                 *dummy; /* Write the value to memory and increment MAD */
 228                 __asm__ __volatile__ ("sync");
 229         }
 230
 231         /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
 232         *mxmr &= 0xCFFFFFC0;
 233 #else
 234         printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
 235         hang();
 236 #endif
 237 }
 238
 239
 240 int
 241 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 242 {
 243         ulong msr;
 244 #ifndef MPC83xx_RESET
 245         ulong addr;
 246 #endif
 247
 248         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 249
 250 #ifdef MPC83xx_RESET
 251         /* Interrupts and MMU off */
 252         __asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
 253
 254         msr &= ~( MSR_EE | MSR_IR | MSR_DR);
 255         __asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
 256
 257         /* enable Reset Control Reg */
 258         immap->reset.rpr = 0x52535445;
 259         __asm__ __volatile__ ("sync");
 260         __asm__ __volatile__ ("isync");
 261
 262         /* confirm Reset Control Reg is enabled */
 263         while(!((immap->reset.rcer) & RCER_CRE));
 264
 265         printf("Resetting the board.");
 266         printf("\n");
 267
 268         udelay(200);
 269
 270         /* perform reset, only one bit */
 271         immap->reset.rcr = RCR_SWHR;
 272
 273 #else   /* ! MPC83xx_RESET */
 274
 275         immap->reset.rmr = RMR_CSRE;    /* Checkstop Reset enable */
 276
 277         /* Interrupts and MMU off */
 278         __asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
 279
 280         msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
 281         __asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
 282
 283         /*
 284          * Trying to execute the next instruction at a non-existing address
 285          * should cause a machine check, resulting in reset
 286          */
 287         addr = CFG_RESET_ADDRESS;
 288
 289         printf("resetting the board.");
 290         printf("\n");
 291         ((void (*)(void)) addr) ();
 292 #endif  /* MPC83xx_RESET */
 293
 294         return 1;
 295 }
 296
 297
 298 /*
 299  * Get timebase clock frequency (like cpu_clk in Hz)
 300  */
 301
 302 unsigned long get_tbclk(void)
 303 {
 304         ulong tbclk;
 305
 306         tbclk = (gd->bus_clk + 3L) / 4L;
 307
 308         return tbclk;
 309 }
 310
 311
 312 #if defined(CONFIG_WATCHDOG)
 313 void watchdog_reset (void)
 314 {
 315         int re_enable = disable_interrupts();
 316
 317         /* Reset the 83xx watchdog */
 318         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 319         immr->wdt.swsrr = 0x556c;
 320         immr->wdt.swsrr = 0xaa39;
 321
 322         if (re_enable)
 323                 enable_interrupts ();
 324 }
 325 #endif
 326
 327 #if defined(CONFIG_OF_LIBFDT)
 328
 329 /*
 330  * "Setter" functions used to add/modify FDT entries.
 331  */
 332 static int fdt_set_eth0(void *blob, int nodeoffset, const char *name, bd_t *bd)
 333 {
 334         /* Fix it up if it exists, don't create it if it doesn't exist */
 335         if (fdt_get_property(blob, nodeoffset, name, 0)) {
 336                 return fdt_setprop(blob, nodeoffset, name, bd->bi_enetaddr, 6);
 337         }
 338         return 0;
 339 }
 340 #ifdef CONFIG_HAS_ETH1
 341 /* second onboard ethernet port */
 342 static int fdt_set_eth1(void *blob, int nodeoffset, const char *name, bd_t *bd)
 343 {
 344         /* Fix it up if it exists, don't create it if it doesn't exist */
 345         if (fdt_get_property(blob, nodeoffset, name, 0)) {
 346                 return fdt_setprop(blob, nodeoffset, name, bd->bi_enet1addr, 6);
 347         }
 348         return 0;
 349 }
 350 #endif
 351 #ifdef CONFIG_HAS_ETH2
 352 /* third onboard ethernet port */
 353 static int fdt_set_eth2(void *blob, int nodeoffset, const char *name, bd_t *bd)
 354 {
 355         /* Fix it up if it exists, don't create it if it doesn't exist */
 356         if (fdt_get_property(blob, nodeoffset, name, 0)) {
 357                 return fdt_setprop(blob, nodeoffset, name, bd->bi_enet2addr, 6);
 358         }
 359         return 0;
 360 }
 361 #endif
 362 #ifdef CONFIG_HAS_ETH3
 363 /* fourth onboard ethernet port */
 364 static int fdt_set_eth3(void *blob, int nodeoffset, const char *name, bd_t *bd)
 365 {
 366         /* Fix it up if it exists, don't create it if it doesn't exist */
 367         if (fdt_get_property(blob, nodeoffset, name, 0)) {
 368                 return fdt_setprop(blob, nodeoffset, name, bd->bi_enet3addr, 6);
 369         }
 370         return 0;
 371 }
 372 #endif
 373
 374 static int fdt_set_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
 375 {
 376         u32  tmp;
 377         /* Create or update the property */
 378         tmp = cpu_to_be32(bd->bi_busfreq);
 379         return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
 380 }
 381
 382 static int fdt_set_tbfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
 383 {
 384         u32  tmp;
 385         /* Create or update the property */
 386         tmp = cpu_to_be32(OF_TBCLK);
 387         return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
 388 }
 389
 390
 391 static int fdt_set_clockfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
 392 {
 393         u32  tmp;
 394         /* Create or update the property */
 395         tmp = cpu_to_be32(gd->core_clk);
 396         return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
 397 }
 398
 399 #ifdef CONFIG_QE
 400 static int fdt_set_qe_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
 401 {
 402         u32  tmp;
 403         /* Create or update the property */
 404         tmp = cpu_to_be32(gd->qe_clk);
 405         return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
 406 }
 407
 408 static int fdt_set_qe_brgfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
 409 {
 410         u32  tmp;
 411         /* Create or update the property */
 412         tmp = cpu_to_be32(gd->brg_clk);
 413         return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
 414 }
 415 #endif
 416
 417 /*
 418  * Fixups to the fdt.
 419  */
 420 static const struct {
 421         char *node;
 422         char *prop;
 423         int (*set_fn)(void *blob, int nodeoffset, const char *name, bd_t *bd);
 424 } fixup_props[] = {
 425         {       "/cpus/" OF_CPU,
 426                 "timebase-frequency",
 427                 fdt_set_tbfreq
 428         },
 429         {       "/cpus/" OF_CPU,
 430                 "bus-frequency",
 431                 fdt_set_busfreq
 432         },
 433         {       "/cpus/" OF_CPU,
 434                 "clock-frequency",
 435                 fdt_set_clockfreq
 436         },
 437         {       "/" OF_SOC,
 438                 "bus-frequency",
 439                 fdt_set_busfreq
 440         },
 441         {       "/" OF_SOC "/serial@4500",
 442                 "clock-frequency",
 443                 fdt_set_busfreq
 444         },
 445         {       "/" OF_SOC "/serial@4600",
 446                 "clock-frequency",
 447                 fdt_set_busfreq
 448         },
 449 #ifdef CONFIG_TSEC1
 450         {       "/" OF_SOC "/ethernet@24000",
 451                 "mac-address",
 452                 fdt_set_eth0
 453         },
 454         {       "/" OF_SOC "/ethernet@24000",
 455                 "local-mac-address",
 456                 fdt_set_eth0
 457         },
 458 #endif
 459 #ifdef CONFIG_TSEC2
 460         {       "/" OF_SOC "/ethernet@25000",
 461                 "mac-address",
 462                 fdt_set_eth1
 463         },
 464         {       "/" OF_SOC "/ethernet@25000",
 465                 "local-mac-address",
 466                 fdt_set_eth1
 467         },
 468 #endif
 469 #ifdef CONFIG_QE
 470         {       "/" OF_QE,
 471                 "brg-frequency",
 472                 fdt_set_qe_brgfreq
 473         },
 474         {       "/" OF_QE,
 475                 "bus-frequency",
 476                 fdt_set_qe_busfreq
 477         },
 478 #ifdef CONFIG_UEC_ETH1
 479 #if CFG_UEC1_UCC_NUM == 0  /* UCC1 */
 480         {       "/" OF_QE "/ucc@2000",
 481                 "mac-address",
 482                 fdt_set_eth0
 483         },
 484         {       "/" OF_QE "/ucc@2000",
 485                 "local-mac-address",
 486                 fdt_set_eth0
 487         },
 488 #elif CFG_UEC1_UCC_NUM == 2  /* UCC3 */
 489         {       "/" OF_QE "/ucc@2200",
 490                 "mac-address",
 491                 fdt_set_eth0
 492         },
 493         {       "/" OF_QE "/ucc@2200",
 494                 "local-mac-address",
 495                 fdt_set_eth0
 496         },
 497 #endif
 498 #endif /* CONFIG_UEC_ETH1 */
 499 #ifdef CONFIG_UEC_ETH2
 500 #if CFG_UEC2_UCC_NUM == 1  /* UCC2 */
 501         {       "/" OF_QE "/ucc@3000",
 502                 "mac-address",
 503                 fdt_set_eth1
 504         },
 505         {       "/" OF_QE "/ucc@3000",
 506                 "local-mac-address",
 507                 fdt_set_eth1
 508         },
 509 #elif CFG_UEC2_UCC_NUM == 3  /* UCC4 */
 510         {       "/" OF_QE "/ucc@3200",
 511                 "mac-address",
 512                 fdt_set_eth1
 513         },
 514         {       "/" OF_QE "/ucc@3200",
 515                 "local-mac-address",
 516                 fdt_set_eth1
 517         },
 518 #endif
 519 #endif /* CONFIG_UEC_ETH2 */
 520 #endif /* CONFIG_QE */
 521 };
 522
 523 void
 524 ft_cpu_setup(void *blob, bd_t *bd)
 525 {
 526         int nodeoffset;
 527         int err;
 528         int j;
 529         int tmp[2];
 530
 531         for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) {
 532                 nodeoffset = fdt_path_offset(blob, fixup_props[j].node);
 533                 if (nodeoffset >= 0) {
 534                         err = fixup_props[j].set_fn(blob, nodeoffset,
 535                                                     fixup_props[j].prop, bd);
 536                         if (err < 0)
 537                                 debug("Problem setting %s = %s: %s\n",
 538                                       fixup_props[j].node, fixup_props[j].prop,
 539                                       fdt_strerror(err));
 540                 } else {
 541                         debug("Couldn't find %s: %s\n",
 542                               fixup_props[j].node, fdt_strerror(nodeoffset));
 543                 }
 544         }
 545
 546         /* update, or add and update /memory node */
 547         nodeoffset = fdt_path_offset(blob, "/memory");
 548         if (nodeoffset < 0) {
 549                 nodeoffset = fdt_add_subnode(blob, 0, "memory");
 550                 if (nodeoffset < 0)
 551                         debug("failed to add /memory node: %s\n",
 552                               fdt_strerror(nodeoffset));
 553         }
 554         if (nodeoffset >= 0) {
 555                 fdt_setprop(blob, nodeoffset, "device_type",
 556                             "memory", sizeof("memory"));
 557                 tmp[0] = cpu_to_be32(bd->bi_memstart);
 558                 tmp[1] = cpu_to_be32(bd->bi_memsize);
 559                 fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp));
 560         }
 561 }
 562 #elif defined(CONFIG_OF_FLAT_TREE)
 563 void
 564 ft_cpu_setup(void *blob, bd_t *bd)
 565 {
 566         u32 *p;
 567         int len;
 568         ulong clock;
 569
 570         clock = bd->bi_busfreq;
 571         p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
 572         if (p != NULL)
 573                 *p = cpu_to_be32(clock);
 574
 575         p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
 576         if (p != NULL)
 577                 *p = cpu_to_be32(clock);
 578
 579         p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
 580         if (p != NULL)
 581                 *p = cpu_to_be32(clock);
 582
 583         p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
 584         if (p != NULL)
 585                 *p = cpu_to_be32(clock);
 586
 587 #ifdef CONFIG_TSEC1
 588         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
 589         if (p != NULL)
 590                 memcpy(p, bd->bi_enetaddr, 6);
 591
 592         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
 593         if (p != NULL)
 594                 memcpy(p, bd->bi_enetaddr, 6);
 595 #endif
 596
 597 #ifdef CONFIG_TSEC2
 598         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
 599         if (p != NULL)
 600                 memcpy(p, bd->bi_enet1addr, 6);
 601
 602         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
 603         if (p != NULL)
 604                 memcpy(p, bd->bi_enet1addr, 6);
 605 #endif
 606
 607 #ifdef CONFIG_UEC_ETH1
 608 #if CFG_UEC1_UCC_NUM == 0  /* UCC1 */
 609         p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
 610         if (p != NULL)
 611                 memcpy(p, bd->bi_enetaddr, 6);
 612
 613         p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
 614         if (p != NULL)
 615                 memcpy(p, bd->bi_enetaddr, 6);
 616 #elif CFG_UEC1_UCC_NUM == 2  /* UCC3 */
 617         p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/mac-address", &len);
 618         if (p != NULL)
 619                 memcpy(p, bd->bi_enetaddr, 6);
 620
 621         p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/local-mac-address", &len);
 622         if (p != NULL)
 623                 memcpy(p, bd->bi_enetaddr, 6);
 624 #endif
 625 #endif
 626
 627 #ifdef CONFIG_UEC_ETH2
 628 #if CFG_UEC2_UCC_NUM == 1  /* UCC2 */
 629         p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
 630         if (p != NULL)
 631                 memcpy(p, bd->bi_enet1addr, 6);
 632
 633         p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
 634         if (p != NULL)
 635                 memcpy(p, bd->bi_enet1addr, 6);
 636 #elif CFG_UEC2_UCC_NUM == 3  /* UCC4 */
 637         p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/mac-address", &len);
 638         if (p != NULL)
 639                 memcpy(p, bd->bi_enet1addr, 6);
 640
 641         p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/local-mac-address", &len);
 642         if (p != NULL)
 643                 memcpy(p, bd->bi_enet1addr, 6);
 644 #endif
 645 #endif
 646 }
 647 #endif
 648
 649 #if defined(CONFIG_DDR_ECC)
 650 void dma_init(void)
 651 {
 652         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 653         volatile dma83xx_t *dma = &immap->dma;
 654         volatile u32 status = swab32(dma->dmasr0);
 655         volatile u32 dmamr0 = swab32(dma->dmamr0);
 656
 657         debug("DMA-init\n");
 658
 659         /* initialize DMASARn, DMADAR and DMAABCRn */
 660         dma->dmadar0 = (u32)0;
 661         dma->dmasar0 = (u32)0;
 662         dma->dmabcr0 = 0;
 663
 664         __asm__ __volatile__ ("sync");
 665         __asm__ __volatile__ ("isync");
 666
 667         /* clear CS bit */
 668         dmamr0 &= ~DMA_CHANNEL_START;
 669         dma->dmamr0 = swab32(dmamr0);
 670         __asm__ __volatile__ ("sync");
 671         __asm__ __volatile__ ("isync");
 672
 673         /* while the channel is busy, spin */
 674         while(status & DMA_CHANNEL_BUSY) {
 675                 status = swab32(dma->dmasr0);
 676         }
 677
 678         debug("DMA-init end\n");
 679 }
 680
 681 uint dma_check(void)
 682 {
 683         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 684         volatile dma83xx_t *dma = &immap->dma;
 685         volatile u32 status = swab32(dma->dmasr0);
 686         volatile u32 byte_count = swab32(dma->dmabcr0);
 687
 688         /* while the channel is busy, spin */
 689         while (status & DMA_CHANNEL_BUSY) {
 690                 status = swab32(dma->dmasr0);
 691         }
 692
 693         if (status & DMA_CHANNEL_TRANSFER_ERROR) {
 694                 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
 695         }
 696
 697         return status;
 698 }
 699
 700 int dma_xfer(void *dest, u32 count, void *src)
 701 {
 702         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 703         volatile dma83xx_t *dma = &immap->dma;
 704         volatile u32 dmamr0;
 705
 706         /* initialize DMASARn, DMADAR and DMAABCRn */
 707         dma->dmadar0 = swab32((u32)dest);
 708         dma->dmasar0 = swab32((u32)src);
 709         dma->dmabcr0 = swab32(count);
 710
 711         __asm__ __volatile__ ("sync");
 712         __asm__ __volatile__ ("isync");
 713
 714         /* init direct transfer, clear CS bit */
 715         dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
 716                         DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
 717                         DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
 718
 719         dma->dmamr0 = swab32(dmamr0);
 720
 721         __asm__ __volatile__ ("sync");
 722         __asm__ __volatile__ ("isync");
 723
 724         /* set CS to start DMA transfer */
 725         dmamr0 |= DMA_CHANNEL_START;
 726         dma->dmamr0 = swab32(dmamr0);
 727         __asm__ __volatile__ ("sync");
 728         __asm__ __volatile__ ("isync");
 729
 730         return ((int)dma_check());
 731 }
 732 #endif /*CONFIG_DDR_ECC*/