cpu/mpc83xx/cpu.c

   1 /*
   2  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * CPU specific code for the MPC83xx family.
  25  *
  26  * Derived from the MPC8260 and MPC85xx.
  27  */
  28
  29 #include <common.h>
  30 #include <watchdog.h>
  31 #include <command.h>
  32 #include <mpc83xx.h>
  33 #include <asm/processor.h>
  34 #if defined(CONFIG_OF_FLAT_TREE)
  35 #include <ft_build.h>
  36 #elif defined(CONFIG_OF_LIBFDT)
  37 #include <libfdt.h>
  38 #include <fdt_support.h>
  39 #endif
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 int checkcpu(void)
  44 {
  45         volatile immap_t *immr;
  46         ulong clock = gd->cpu_clk;
  47         u32 pvr = get_pvr();
  48         u32 spridr;
  49         char buf[32];
  50
  51         immr = (immap_t *)CFG_IMMR;
  52
  53         puts("CPU:   ");
  54
  55         switch (pvr & 0xffff0000) {
  56                 case PVR_E300C1:
  57                         printf("e300c1, ");
  58                         break;
  59
  60                 case PVR_E300C2:
  61                         printf("e300c2, ");
  62                         break;
  63
  64                 case PVR_E300C3:
  65                         printf("e300c3, ");
  66                         break;
  67
  68                 case PVR_E300C4:
  69                         printf("e300c4, ");
  70                         break;
  71
  72                 default:
  73                         printf("Unknown core, ");
  74         }
  75
  76         spridr = immr->sysconf.spridr;
  77         switch(spridr) {
  78         case SPR_8349E_REV10:
  79         case SPR_8349E_REV11:
  80         case SPR_8349E_REV31:
  81                 puts("MPC8349E, ");
  82                 break;
  83         case SPR_8349_REV10:
  84         case SPR_8349_REV11:
  85         case SPR_8349_REV31:
  86                 puts("MPC8349, ");
  87                 break;
  88         case SPR_8347E_REV10_TBGA:
  89         case SPR_8347E_REV11_TBGA:
  90         case SPR_8347E_REV31_TBGA:
  91         case SPR_8347E_REV10_PBGA:
  92         case SPR_8347E_REV11_PBGA:
  93         case SPR_8347E_REV31_PBGA:
  94                 puts("MPC8347E, ");
  95                 break;
  96         case SPR_8347_REV10_TBGA:
  97         case SPR_8347_REV11_TBGA:
  98         case SPR_8347_REV31_TBGA:
  99         case SPR_8347_REV10_PBGA:
 100         case SPR_8347_REV11_PBGA:
 101         case SPR_8347_REV31_PBGA:
 102                 puts("MPC8347, ");
 103                 break;
 104         case SPR_8343E_REV10:
 105         case SPR_8343E_REV11:
 106         case SPR_8343E_REV31:
 107                 puts("MPC8343E, ");
 108                 break;
 109         case SPR_8343_REV10:
 110         case SPR_8343_REV11:
 111         case SPR_8343_REV31:
 112                 puts("MPC8343, ");
 113                 break;
 114         case SPR_8360E_REV10:
 115         case SPR_8360E_REV11:
 116         case SPR_8360E_REV12:
 117         case SPR_8360E_REV20:
 118         case SPR_8360E_REV21:
 119                 puts("MPC8360E, ");
 120                 break;
 121         case SPR_8360_REV10:
 122         case SPR_8360_REV11:
 123         case SPR_8360_REV12:
 124         case SPR_8360_REV20:
 125         case SPR_8360_REV21:
 126                 puts("MPC8360, ");
 127                 break;
 128         case SPR_8323E_REV10:
 129         case SPR_8323E_REV11:
 130                 puts("MPC8323E, ");
 131                 break;
 132         case SPR_8323_REV10:
 133         case SPR_8323_REV11:
 134                 puts("MPC8323, ");
 135                 break;
 136         case SPR_8321E_REV10:
 137         case SPR_8321E_REV11:
 138                 puts("MPC8321E, ");
 139                 break;
 140         case SPR_8321_REV10:
 141         case SPR_8321_REV11:
 142                 puts("MPC8321, ");
 143                 break;
 144         case SPR_8311_REV10:
 145                 puts("MPC8311, ");
 146                 break;
 147         case SPR_8311E_REV10:
 148                 puts("MPC8311E, ");
 149                 break;
 150         case SPR_8313_REV10:
 151                 puts("MPC8313, ");
 152                 break;
 153         case SPR_8313E_REV10:
 154                 puts("MPC8313E, ");
 155                 break;
 156         case SPR_8315E_REV10:
 157                 puts("MPC8315E, ");
 158                 break;
 159         case SPR_8315_REV10:
 160                 puts("MPC8315, ");
 161                 break;
 162         case SPR_8314E_REV10:
 163                 puts("MPC8314E, ");
 164                 break;
 165         case SPR_8314_REV10:
 166                 puts("MPC8314, ");
 167                 break;
 168         case SPR_8379E_REV10:
 169                 puts("MPC8379E, ");
 170                 break;
 171         case SPR_8379_REV10:
 172                 puts("MPC8379, ");
 173                 break;
 174         case SPR_8378E_REV10:
 175                 puts("MPC8378E, ");
 176                 break;
 177         case SPR_8378_REV10:
 178                 puts("MPC8378, ");
 179                 break;
 180         case SPR_8377E_REV10:
 181                 puts("MPC8377E, ");
 182                 break;
 183         case SPR_8377_REV10:
 184                 puts("MPC8377, ");
 185                 break;
 186         default:
 187                 printf("Rev: Unknown revision number:%08x\n"
 188                         "Warning: Unsupported cpu revision!\n",spridr);
 189                 return 0;
 190         }
 191
 192 #if defined(CONFIG_MPC834X)
 193         /* Multiple revisons of 834x processors may have the same SPRIDR value.
 194          * So use PVR to identify the revision number.
 195          */
 196         printf("Rev: %02x at %s MHz", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
 197 #else
 198         printf("Rev: %02x at %s MHz", spridr & 0x0000FFFF, strmhz(buf, clock));
 199 #endif
 200         printf(", CSB: %4d MHz\n", gd->csb_clk / 1000000);
 201
 202         return 0;
 203 }
 204
 205
 206 /*
 207  * Program a UPM with the code supplied in the table.
 208  *
 209  * The 'dummy' variable is used to increment the MAD. 'dummy' is
 210  * supposed to be a pointer to the memory of the device being
 211  * programmed by the UPM.  The data in the MDR is written into
 212  * memory and the MAD is incremented every time there's a read
 213  * from 'dummy'. Unfortunately, the current prototype for this
 214  * function doesn't allow for passing the address of this
 215  * device, and changing the prototype will break a number lots
 216  * of other code, so we need to use a round-about way of finding
 217  * the value for 'dummy'.
 218  *
 219  * The value can be extracted from the base address bits of the
 220  * Base Register (BR) associated with the specific UPM.  To find
 221  * that BR, we need to scan all 8 BRs until we find the one that
 222  * has its MSEL bits matching the UPM we want.  Once we know the
 223  * right BR, we can extract the base address bits from it.
 224  *
 225  * The MxMR and the BR and OR of the chosen bank should all be
 226  * configured before calling this function.
 227  *
 228  * Parameters:
 229  * upm: 0=UPMA, 1=UPMB, 2=UPMC
 230  * table: Pointer to an array of values to program
 231  * size: Number of elements in the array.  Must be 64 or less.
 232  */
 233 void upmconfig (uint upm, uint *table, uint size)
 234 {
 235 #if defined(CONFIG_MPC834X)
 236         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 237         volatile lbus83xx_t *lbus = &immap->lbus;
 238         volatile uchar *dummy = NULL;
 239         const u32 msel = (upm + 4) << BR_MSEL_SHIFT;    /* What the MSEL field in BRn should be */
 240         volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
 241         uint i;
 242
 243         /* Scan all the banks to determine the base address of the device */
 244         for (i = 0; i < 8; i++) {
 245                 if ((lbus->bank[i].br & BR_MSEL) == msel) {
 246                         dummy = (uchar *) (lbus->bank[i].br & BR_BA);
 247                         break;
 248                 }
 249         }
 250
 251         if (!dummy) {
 252                 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
 253                 hang();
 254         }
 255
 256         /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
 257         *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
 258
 259         for (i = 0; i < size; i++) {
 260                 lbus->mdr = table[i];
 261                 __asm__ __volatile__ ("sync");
 262                 *dummy; /* Write the value to memory and increment MAD */
 263                 __asm__ __volatile__ ("sync");
 264         }
 265
 266         /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
 267         *mxmr &= 0xCFFFFFC0;
 268 #else
 269         printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
 270         hang();
 271 #endif
 272 }
 273
 274
 275 int
 276 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 277 {
 278         ulong msr;
 279 #ifndef MPC83xx_RESET
 280         ulong addr;
 281 #endif
 282
 283         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 284
 285 #ifdef MPC83xx_RESET
 286         /* Interrupts and MMU off */
 287         __asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
 288
 289         msr &= ~( MSR_EE | MSR_IR | MSR_DR);
 290         __asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
 291
 292         /* enable Reset Control Reg */
 293         immap->reset.rpr = 0x52535445;
 294         __asm__ __volatile__ ("sync");
 295         __asm__ __volatile__ ("isync");
 296
 297         /* confirm Reset Control Reg is enabled */
 298         while(!((immap->reset.rcer) & RCER_CRE));
 299
 300         printf("Resetting the board.");
 301         printf("\n");
 302
 303         udelay(200);
 304
 305         /* perform reset, only one bit */
 306         immap->reset.rcr = RCR_SWHR;
 307
 308 #else   /* ! MPC83xx_RESET */
 309
 310         immap->reset.rmr = RMR_CSRE;    /* Checkstop Reset enable */
 311
 312         /* Interrupts and MMU off */
 313         __asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
 314
 315         msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
 316         __asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
 317
 318         /*
 319          * Trying to execute the next instruction at a non-existing address
 320          * should cause a machine check, resulting in reset
 321          */
 322         addr = CFG_RESET_ADDRESS;
 323
 324         printf("resetting the board.");
 325         printf("\n");
 326         ((void (*)(void)) addr) ();
 327 #endif  /* MPC83xx_RESET */
 328
 329         return 1;
 330 }
 331
 332
 333 /*
 334  * Get timebase clock frequency (like cpu_clk in Hz)
 335  */
 336
 337 unsigned long get_tbclk(void)
 338 {
 339         ulong tbclk;
 340
 341         tbclk = (gd->bus_clk + 3L) / 4L;
 342
 343         return tbclk;
 344 }
 345
 346
 347 #if defined(CONFIG_WATCHDOG)
 348 void watchdog_reset (void)
 349 {
 350         int re_enable = disable_interrupts();
 351
 352         /* Reset the 83xx watchdog */
 353         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 354         immr->wdt.swsrr = 0x556c;
 355         immr->wdt.swsrr = 0xaa39;
 356
 357         if (re_enable)
 358                 enable_interrupts ();
 359 }
 360 #endif
 361
 362 #if defined(CONFIG_OF_LIBFDT)
 363
 364 /*
 365  * "Setter" functions used to add/modify FDT entries.
 366  */
 367 static int fdt_set_eth0(void *blob, int nodeoffset, const char *name, bd_t *bd)
 368 {
 369         /* Fix it up if it exists, don't create it if it doesn't exist */
 370         if (fdt_get_property(blob, nodeoffset, name, 0)) {
 371                 return fdt_setprop(blob, nodeoffset, name, bd->bi_enetaddr, 6);
 372         }
 373         return 0;
 374 }
 375 #ifdef CONFIG_HAS_ETH1
 376 /* second onboard ethernet port */
 377 static int fdt_set_eth1(void *blob, int nodeoffset, const char *name, bd_t *bd)
 378 {
 379         /* Fix it up if it exists, don't create it if it doesn't exist */
 380         if (fdt_get_property(blob, nodeoffset, name, 0)) {
 381                 return fdt_setprop(blob, nodeoffset, name, bd->bi_enet1addr, 6);
 382         }
 383         return 0;
 384 }
 385 #endif
 386 #ifdef CONFIG_HAS_ETH2
 387 /* third onboard ethernet port */
 388 static int fdt_set_eth2(void *blob, int nodeoffset, const char *name, bd_t *bd)
 389 {
 390         /* Fix it up if it exists, don't create it if it doesn't exist */
 391         if (fdt_get_property(blob, nodeoffset, name, 0)) {
 392                 return fdt_setprop(blob, nodeoffset, name, bd->bi_enet2addr, 6);
 393         }
 394         return 0;
 395 }
 396 #endif
 397 #ifdef CONFIG_HAS_ETH3
 398 /* fourth onboard ethernet port */
 399 static int fdt_set_eth3(void *blob, int nodeoffset, const char *name, bd_t *bd)
 400 {
 401         /* Fix it up if it exists, don't create it if it doesn't exist */
 402         if (fdt_get_property(blob, nodeoffset, name, 0)) {
 403                 return fdt_setprop(blob, nodeoffset, name, bd->bi_enet3addr, 6);
 404         }
 405         return 0;
 406 }
 407 #endif
 408
 409 static int fdt_set_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
 410 {
 411         u32  tmp;
 412         /* Create or update the property */
 413         tmp = cpu_to_be32(bd->bi_busfreq);
 414         return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
 415 }
 416
 417 static int fdt_set_tbfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
 418 {
 419         u32  tmp;
 420         /* Create or update the property */
 421         tmp = cpu_to_be32(OF_TBCLK);
 422         return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
 423 }
 424
 425
 426 static int fdt_set_clockfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
 427 {
 428         u32  tmp;
 429         /* Create or update the property */
 430         tmp = cpu_to_be32(gd->core_clk);
 431         return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
 432 }
 433
 434 #ifdef CONFIG_QE
 435 static int fdt_set_qe_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
 436 {
 437         u32  tmp;
 438         /* Create or update the property */
 439         tmp = cpu_to_be32(gd->qe_clk);
 440         return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
 441 }
 442
 443 static int fdt_set_qe_brgfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
 444 {
 445         u32  tmp;
 446         /* Create or update the property */
 447         tmp = cpu_to_be32(gd->brg_clk);
 448         return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
 449 }
 450 #endif
 451
 452 /*
 453  * Fixups to the fdt.
 454  */
 455 static const struct {
 456         char *node;
 457         char *prop;
 458         int (*set_fn)(void *blob, int nodeoffset, const char *name, bd_t *bd);
 459 } fixup_props[] = {
 460         {       "/cpus/" OF_CPU,
 461                 "timebase-frequency",
 462                 fdt_set_tbfreq
 463         },
 464         {       "/cpus/" OF_CPU,
 465                 "bus-frequency",
 466                 fdt_set_busfreq
 467         },
 468         {       "/cpus/" OF_CPU,
 469                 "clock-frequency",
 470                 fdt_set_clockfreq
 471         },
 472         {       "/" OF_SOC,
 473                 "bus-frequency",
 474                 fdt_set_busfreq
 475         },
 476         {       "/" OF_SOC "/serial@4500",
 477                 "clock-frequency",
 478                 fdt_set_busfreq
 479         },
 480         {       "/" OF_SOC "/serial@4600",
 481                 "clock-frequency",
 482                 fdt_set_busfreq
 483         },
 484 #ifdef CONFIG_TSEC1
 485         {       "/" OF_SOC "/ethernet@24000",
 486                 "mac-address",
 487                 fdt_set_eth0
 488         },
 489         {       "/" OF_SOC "/ethernet@24000",
 490                 "local-mac-address",
 491                 fdt_set_eth0
 492         },
 493 #endif
 494 #ifdef CONFIG_TSEC2
 495         {       "/" OF_SOC "/ethernet@25000",
 496                 "mac-address",
 497                 fdt_set_eth1
 498         },
 499         {       "/" OF_SOC "/ethernet@25000",
 500                 "local-mac-address",
 501                 fdt_set_eth1
 502         },
 503 #endif
 504 #ifdef CONFIG_QE
 505         {       "/" OF_QE,
 506                 "brg-frequency",
 507                 fdt_set_qe_brgfreq
 508         },
 509         {       "/" OF_QE,
 510                 "bus-frequency",
 511                 fdt_set_qe_busfreq
 512         },
 513 #ifdef CONFIG_UEC_ETH1
 514 #if CFG_UEC1_UCC_NUM == 0  /* UCC1 */
 515         {       "/" OF_QE "/ucc@2000",
 516                 "mac-address",
 517                 fdt_set_eth0
 518         },
 519         {       "/" OF_QE "/ucc@2000",
 520                 "local-mac-address",
 521                 fdt_set_eth0
 522         },
 523 #elif CFG_UEC1_UCC_NUM == 2  /* UCC3 */
 524         {       "/" OF_QE "/ucc@2200",
 525                 "mac-address",
 526                 fdt_set_eth0
 527         },
 528         {       "/" OF_QE "/ucc@2200",
 529                 "local-mac-address",
 530                 fdt_set_eth0
 531         },
 532 #endif
 533 #endif /* CONFIG_UEC_ETH1 */
 534 #ifdef CONFIG_UEC_ETH2
 535 #if CFG_UEC2_UCC_NUM == 1  /* UCC2 */
 536         {       "/" OF_QE "/ucc@3000",
 537                 "mac-address",
 538                 fdt_set_eth1
 539         },
 540         {       "/" OF_QE "/ucc@3000",
 541                 "local-mac-address",
 542                 fdt_set_eth1
 543         },
 544 #elif CFG_UEC2_UCC_NUM == 3  /* UCC4 */
 545         {       "/" OF_QE "/ucc@3200",
 546                 "mac-address",
 547                 fdt_set_eth1
 548         },
 549         {       "/" OF_QE "/ucc@3200",
 550                 "local-mac-address",
 551                 fdt_set_eth1
 552         },
 553 #endif
 554 #endif /* CONFIG_UEC_ETH2 */
 555 #endif /* CONFIG_QE */
 556 };
 557
 558 void
 559 ft_cpu_setup(void *blob, bd_t *bd)
 560 {
 561         int nodeoffset;
 562         int err;
 563         int j;
 564
 565         for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) {
 566                 nodeoffset = fdt_path_offset(blob, fixup_props[j].node);
 567                 if (nodeoffset >= 0) {
 568                         err = fixup_props[j].set_fn(blob, nodeoffset,
 569                                                     fixup_props[j].prop, bd);
 570                         if (err < 0)
 571                                 debug("Problem setting %s = %s: %s\n",
 572                                       fixup_props[j].node, fixup_props[j].prop,
 573                                       fdt_strerror(err));
 574                 } else {
 575                         debug("Couldn't find %s: %s\n",
 576                               fixup_props[j].node, fdt_strerror(nodeoffset));
 577                 }
 578         }
 579
 580         fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 581 }
 582 #elif defined(CONFIG_OF_FLAT_TREE)
 583 void
 584 ft_cpu_setup(void *blob, bd_t *bd)
 585 {
 586         u32 *p;
 587         int len;
 588         ulong clock;
 589
 590         clock = bd->bi_busfreq;
 591         p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
 592         if (p != NULL)
 593                 *p = cpu_to_be32(clock);
 594
 595         p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
 596         if (p != NULL)
 597                 *p = cpu_to_be32(clock);
 598
 599         p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
 600         if (p != NULL)
 601                 *p = cpu_to_be32(clock);
 602
 603         p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
 604         if (p != NULL)
 605                 *p = cpu_to_be32(clock);
 606
 607 #ifdef CONFIG_TSEC1
 608         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
 609         if (p != NULL)
 610                 memcpy(p, bd->bi_enetaddr, 6);
 611
 612         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
 613         if (p != NULL)
 614                 memcpy(p, bd->bi_enetaddr, 6);
 615 #endif
 616
 617 #ifdef CONFIG_TSEC2
 618         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
 619         if (p != NULL)
 620                 memcpy(p, bd->bi_enet1addr, 6);
 621
 622         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
 623         if (p != NULL)
 624                 memcpy(p, bd->bi_enet1addr, 6);
 625 #endif
 626
 627 #ifdef CONFIG_UEC_ETH1
 628 #if CFG_UEC1_UCC_NUM == 0  /* UCC1 */
 629         p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
 630         if (p != NULL)
 631                 memcpy(p, bd->bi_enetaddr, 6);
 632
 633         p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
 634         if (p != NULL)
 635                 memcpy(p, bd->bi_enetaddr, 6);
 636 #elif CFG_UEC1_UCC_NUM == 2  /* UCC3 */
 637         p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/mac-address", &len);
 638         if (p != NULL)
 639                 memcpy(p, bd->bi_enetaddr, 6);
 640
 641         p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/local-mac-address", &len);
 642         if (p != NULL)
 643                 memcpy(p, bd->bi_enetaddr, 6);
 644 #endif
 645 #endif
 646
 647 #ifdef CONFIG_UEC_ETH2
 648 #if CFG_UEC2_UCC_NUM == 1  /* UCC2 */
 649         p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
 650         if (p != NULL)
 651                 memcpy(p, bd->bi_enet1addr, 6);
 652
 653         p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
 654         if (p != NULL)
 655                 memcpy(p, bd->bi_enet1addr, 6);
 656 #elif CFG_UEC2_UCC_NUM == 3  /* UCC4 */
 657         p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/mac-address", &len);
 658         if (p != NULL)
 659                 memcpy(p, bd->bi_enet1addr, 6);
 660
 661         p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/local-mac-address", &len);
 662         if (p != NULL)
 663                 memcpy(p, bd->bi_enet1addr, 6);
 664 #endif
 665 #endif
 666 }
 667 #endif
 668
 669 #if defined(CONFIG_DDR_ECC)
 670 void dma_init(void)
 671 {
 672         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 673         volatile dma83xx_t *dma = &immap->dma;
 674         volatile u32 status = swab32(dma->dmasr0);
 675         volatile u32 dmamr0 = swab32(dma->dmamr0);
 676
 677         debug("DMA-init\n");
 678
 679         /* initialize DMASARn, DMADAR and DMAABCRn */
 680         dma->dmadar0 = (u32)0;
 681         dma->dmasar0 = (u32)0;
 682         dma->dmabcr0 = 0;
 683
 684         __asm__ __volatile__ ("sync");
 685         __asm__ __volatile__ ("isync");
 686
 687         /* clear CS bit */
 688         dmamr0 &= ~DMA_CHANNEL_START;
 689         dma->dmamr0 = swab32(dmamr0);
 690         __asm__ __volatile__ ("sync");
 691         __asm__ __volatile__ ("isync");
 692
 693         /* while the channel is busy, spin */
 694         while(status & DMA_CHANNEL_BUSY) {
 695                 status = swab32(dma->dmasr0);
 696         }
 697
 698         debug("DMA-init end\n");
 699 }
 700
 701 uint dma_check(void)
 702 {
 703         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 704         volatile dma83xx_t *dma = &immap->dma;
 705         volatile u32 status = swab32(dma->dmasr0);
 706         volatile u32 byte_count = swab32(dma->dmabcr0);
 707
 708         /* while the channel is busy, spin */
 709         while (status & DMA_CHANNEL_BUSY) {
 710                 status = swab32(dma->dmasr0);
 711         }
 712
 713         if (status & DMA_CHANNEL_TRANSFER_ERROR) {
 714                 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
 715         }
 716
 717         return status;
 718 }
 719
 720 int dma_xfer(void *dest, u32 count, void *src)
 721 {
 722         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 723         volatile dma83xx_t *dma = &immap->dma;
 724         volatile u32 dmamr0;
 725
 726         /* initialize DMASARn, DMADAR and DMAABCRn */
 727         dma->dmadar0 = swab32((u32)dest);
 728         dma->dmasar0 = swab32((u32)src);
 729         dma->dmabcr0 = swab32(count);
 730
 731         __asm__ __volatile__ ("sync");
 732         __asm__ __volatile__ ("isync");
 733
 734         /* init direct transfer, clear CS bit */
 735         dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
 736                         DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
 737                         DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
 738
 739         dma->dmamr0 = swab32(dmamr0);
 740
 741         __asm__ __volatile__ ("sync");
 742         __asm__ __volatile__ ("isync");
 743
 744         /* set CS to start DMA transfer */
 745         dmamr0 |= DMA_CHANNEL_START;
 746         dma->dmamr0 = swab32(dmamr0);
 747         __asm__ __volatile__ ("sync");
 748         __asm__ __volatile__ ("isync");
 749
 750         return ((int)dma_check());
 751 }
 752 #endif /*CONFIG_DDR_ECC*/