cpu/mpc83xx/cpu.c

   1 /*
   2  * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * CPU specific code for the MPC83xx family.
  25  *
  26  * Derived from the MPC8260 and MPC85xx.
  27  */
  28
  29 #include <common.h>
  30 #include <watchdog.h>
  31 #include <command.h>
  32 #include <mpc83xx.h>
  33 #include <asm/processor.h>
  34 #if defined(CONFIG_OF_FLAT_TREE)
  35 #include <ft_build.h>
  36 #endif
  37 #if defined(CONFIG_OF_LIBFDT)
  38 #include <libfdt.h>
  39 #include <libfdt_env.h>
  40 #endif
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44
  45 int checkcpu(void)
  46 {
  47         volatile immap_t *immr;
  48         ulong clock = gd->cpu_clk;
  49         u32 pvr = get_pvr();
  50         u32 spridr;
  51         char buf[32];
  52
  53         immr = (immap_t *)CFG_IMMR;
  54
  55         puts("CPU:   ");
  56
  57         switch (pvr & 0xffff0000) {
  58                 case PVR_E300C1:
  59                         printf("e300c1, ");
  60                         break;
  61
  62                 case PVR_E300C2:
  63                         printf("e300c2, ");
  64                         break;
  65
  66                 case PVR_E300C3:
  67                         printf("e300c3, ");
  68                         break;
  69
  70                 default:
  71                         printf("Unknown core, ");
  72         }
  73
  74         spridr = immr->sysconf.spridr;
  75         switch(spridr) {
  76         case SPR_8349E_REV10:
  77         case SPR_8349E_REV11:
  78         case SPR_8349E_REV31:
  79                 puts("MPC8349E, ");
  80                 break;
  81         case SPR_8349_REV10:
  82         case SPR_8349_REV11:
  83         case SPR_8349_REV31:
  84                 puts("MPC8349, ");
  85                 break;
  86         case SPR_8347E_REV10_TBGA:
  87         case SPR_8347E_REV11_TBGA:
  88         case SPR_8347E_REV31_TBGA:
  89         case SPR_8347E_REV10_PBGA:
  90         case SPR_8347E_REV11_PBGA:
  91         case SPR_8347E_REV31_PBGA:
  92                 puts("MPC8347E, ");
  93                 break;
  94         case SPR_8347_REV10_TBGA:
  95         case SPR_8347_REV11_TBGA:
  96         case SPR_8347_REV31_TBGA:
  97         case SPR_8347_REV10_PBGA:
  98         case SPR_8347_REV11_PBGA:
  99         case SPR_8347_REV31_PBGA:
 100                 puts("MPC8347, ");
 101                 break;
 102         case SPR_8343E_REV10:
 103         case SPR_8343E_REV11:
 104         case SPR_8343E_REV31:
 105                 puts("MPC8343E, ");
 106                 break;
 107         case SPR_8343_REV10:
 108         case SPR_8343_REV11:
 109         case SPR_8343_REV31:
 110                 puts("MPC8343, ");
 111                 break;
 112         case SPR_8360E_REV10:
 113         case SPR_8360E_REV11:
 114         case SPR_8360E_REV12:
 115         case SPR_8360E_REV20:
 116                 puts("MPC8360E, ");
 117                 break;
 118         case SPR_8360_REV10:
 119         case SPR_8360_REV11:
 120         case SPR_8360_REV12:
 121         case SPR_8360_REV20:
 122                 puts("MPC8360, ");
 123                 break;
 124         case SPR_8323E_REV10:
 125         case SPR_8323E_REV11:
 126                 puts("MPC8323E, ");
 127                 break;
 128         case SPR_8323_REV10:
 129         case SPR_8323_REV11:
 130                 puts("MPC8323, ");
 131                 break;
 132         case SPR_8321E_REV10:
 133         case SPR_8321E_REV11:
 134                 puts("MPC8321E, ");
 135                 break;
 136         case SPR_8321_REV10:
 137         case SPR_8321_REV11:
 138                 puts("MPC8321, ");
 139                 break;
 140         case SPR_8311_REV10:
 141                 puts("MPC8311, ");
 142                 break;
 143         case SPR_8311E_REV10:
 144                 puts("MPC8311E, ");
 145                 break;
 146         case SPR_8313_REV10:
 147                 puts("MPC8313, ");
 148                 break;
 149         case SPR_8313E_REV10:
 150                 puts("MPC8313E, ");
 151                 break;
 152         default:
 153                 puts("Rev: Unknown revision number.\nWarning: Unsupported cpu revision!\n");
 154                 return 0;
 155         }
 156
 157 #if defined(CONFIG_MPC834X)
 158         /* Multiple revisons of 834x processors may have the same SPRIDR value.
 159          * So use PVR to identify the revision number.
 160          */
 161         printf("Rev: %02x at %s MHz", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
 162 #else
 163         printf("Rev: %02x at %s MHz", spridr & 0x0000FFFF, strmhz(buf, clock));
 164 #endif
 165         printf(", CSB: %4d MHz\n", gd->csb_clk / 1000000);
 166
 167         return 0;
 168 }
 169
 170
 171 /*
 172  * Program a UPM with the code supplied in the table.
 173  *
 174  * The 'dummy' variable is used to increment the MAD. 'dummy' is
 175  * supposed to be a pointer to the memory of the device being
 176  * programmed by the UPM.  The data in the MDR is written into
 177  * memory and the MAD is incremented every time there's a read
 178  * from 'dummy'. Unfortunately, the current prototype for this
 179  * function doesn't allow for passing the address of this
 180  * device, and changing the prototype will break a number lots
 181  * of other code, so we need to use a round-about way of finding
 182  * the value for 'dummy'.
 183  *
 184  * The value can be extracted from the base address bits of the
 185  * Base Register (BR) associated with the specific UPM.  To find
 186  * that BR, we need to scan all 8 BRs until we find the one that
 187  * has its MSEL bits matching the UPM we want.  Once we know the
 188  * right BR, we can extract the base address bits from it.
 189  *
 190  * The MxMR and the BR and OR of the chosen bank should all be
 191  * configured before calling this function.
 192  *
 193  * Parameters:
 194  * upm: 0=UPMA, 1=UPMB, 2=UPMC
 195  * table: Pointer to an array of values to program
 196  * size: Number of elements in the array.  Must be 64 or less.
 197  */
 198 void upmconfig (uint upm, uint *table, uint size)
 199 {
 200 #if defined(CONFIG_MPC834X)
 201         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 202         volatile lbus83xx_t *lbus = &immap->lbus;
 203         volatile uchar *dummy = NULL;
 204         const u32 msel = (upm + 4) << BR_MSEL_SHIFT;    /* What the MSEL field in BRn should be */
 205         volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
 206         uint i;
 207
 208         /* Scan all the banks to determine the base address of the device */
 209         for (i = 0; i < 8; i++) {
 210                 if ((lbus->bank[i].br & BR_MSEL) == msel) {
 211                         dummy = (uchar *) (lbus->bank[i].br & BR_BA);
 212                         break;
 213                 }
 214         }
 215
 216         if (!dummy) {
 217                 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
 218                 hang();
 219         }
 220
 221         /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
 222         *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
 223
 224         for (i = 0; i < size; i++) {
 225                 lbus->mdr = table[i];
 226                 __asm__ __volatile__ ("sync");
 227                 *dummy; /* Write the value to memory and increment MAD */
 228                 __asm__ __volatile__ ("sync");
 229         }
 230
 231         /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
 232         *mxmr &= 0xCFFFFFC0;
 233 #else
 234         printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
 235         hang();
 236 #endif
 237 }
 238
 239
 240 int
 241 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 242 {
 243         ulong msr;
 244 #ifndef MPC83xx_RESET
 245         ulong addr;
 246 #endif
 247
 248         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 249
 250 #ifdef MPC83xx_RESET
 251         /* Interrupts and MMU off */
 252         __asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
 253
 254         msr &= ~( MSR_EE | MSR_IR | MSR_DR);
 255         __asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
 256
 257         /* enable Reset Control Reg */
 258         immap->reset.rpr = 0x52535445;
 259         __asm__ __volatile__ ("sync");
 260         __asm__ __volatile__ ("isync");
 261
 262         /* confirm Reset Control Reg is enabled */
 263         while(!((immap->reset.rcer) & RCER_CRE));
 264
 265         printf("Resetting the board.");
 266         printf("\n");
 267
 268         udelay(200);
 269
 270         /* perform reset, only one bit */
 271         immap->reset.rcr = RCR_SWHR;
 272
 273 #else   /* ! MPC83xx_RESET */
 274
 275         immap->reset.rmr = RMR_CSRE;    /* Checkstop Reset enable */
 276
 277         /* Interrupts and MMU off */
 278         __asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
 279
 280         msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
 281         __asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
 282
 283         /*
 284          * Trying to execute the next instruction at a non-existing address
 285          * should cause a machine check, resulting in reset
 286          */
 287         addr = CFG_RESET_ADDRESS;
 288
 289         printf("resetting the board.");
 290         printf("\n");
 291         ((void (*)(void)) addr) ();
 292 #endif  /* MPC83xx_RESET */
 293
 294         return 1;
 295 }
 296
 297
 298 /*
 299  * Get timebase clock frequency (like cpu_clk in Hz)
 300  */
 301
 302 unsigned long get_tbclk(void)
 303 {
 304         ulong tbclk;
 305
 306         tbclk = (gd->bus_clk + 3L) / 4L;
 307
 308         return tbclk;
 309 }
 310
 311
 312 #if defined(CONFIG_WATCHDOG)
 313 void watchdog_reset (void)
 314 {
 315         int re_enable = disable_interrupts();
 316
 317         /* Reset the 83xx watchdog */
 318         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 319         immr->wdt.swsrr = 0x556c;
 320         immr->wdt.swsrr = 0xaa39;
 321
 322         if (re_enable)
 323                 enable_interrupts ();
 324 }
 325 #endif
 326
 327 #if defined(CONFIG_OF_LIBFDT)
 328
 329 /*
 330  * "Setter" functions used to add/modify FDT entries.
 331  */
 332 static int fdt_set_eth0(void *fdt, int nodeoffset, const char *name, bd_t *bd)
 333 {
 334         /*
 335          * Fix it up if it exists, don't create it if it doesn't exist.
 336          */
 337         if (fdt_get_property(fdt, nodeoffset, name, 0)) {
 338                 return fdt_setprop(fdt, nodeoffset, name, bd->bi_enetaddr, 6);
 339         }
 340         return -FDT_ERR_NOTFOUND;
 341 }
 342 #ifdef CONFIG_HAS_ETH1
 343 /* second onboard ethernet port */
 344 static int fdt_set_eth1(void *fdt, int nodeoffset, const char *name, bd_t *bd)
 345 {
 346         /*
 347          * Fix it up if it exists, don't create it if it doesn't exist.
 348          */
 349         if (fdt_get_property(fdt, nodeoffset, name, 0)) {
 350                 return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet1addr, 6);
 351         }
 352         return -FDT_ERR_NOTFOUND;
 353 }
 354 #endif
 355 #ifdef CONFIG_HAS_ETH2
 356 /* third onboard ethernet port */
 357 static int fdt_set_eth2(void *fdt, int nodeoffset, const char *name, bd_t *bd)
 358 {
 359         /*
 360          * Fix it up if it exists, don't create it if it doesn't exist.
 361          */
 362         if (fdt_get_property(fdt, nodeoffset, name, 0)) {
 363                 return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet2addr, 6);
 364         }
 365         return -FDT_ERR_NOTFOUND;
 366 }
 367 #endif
 368 #ifdef CONFIG_HAS_ETH3
 369 /* fourth onboard ethernet port */
 370 static int fdt_set_eth3(void *fdt, int nodeoffset, const char *name, bd_t *bd)
 371 {
 372         /*
 373          * Fix it up if it exists, don't create it if it doesn't exist.
 374          */
 375         if (fdt_get_property(fdt, nodeoffset, name, 0)) {
 376                 return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet3addr, 6);
 377         }
 378         return -FDT_ERR_NOTFOUND;
 379 }
 380 #endif
 381
 382 static int fdt_set_busfreq(void *fdt, int nodeoffset, const char *name, bd_t *bd)
 383 {
 384         u32  tmp;
 385         /*
 386          * Create or update the property.
 387          */
 388         tmp = cpu_to_be32(bd->bi_busfreq);
 389         return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
 390 }
 391
 392 /*
 393  * Fixups to the fdt.  If "create" is TRUE, the node is created
 394  * unconditionally.  If "create" is FALSE, the node is updated
 395  * only if it already exists.
 396  */
 397 static const struct {
 398         char *node;
 399         char *prop;
 400         int (*set_fn)(void *fdt, int nodeoffset, const char *name, bd_t *bd);
 401 } fixup_props[] = {
 402         {       "/cpus/" OF_CPU,
 403                  "bus-frequency",
 404                 fdt_set_busfreq
 405         },
 406         {       "/cpus/" OF_SOC,
 407                 "bus-frequency",
 408                 fdt_set_busfreq
 409         },
 410         {       "/" OF_SOC "/serial@4500/",
 411                 "clock-frequency",
 412                 fdt_set_busfreq
 413         },
 414         {       "/" OF_SOC "/serial@4600/",
 415                 "clock-frequency",
 416                 fdt_set_busfreq
 417         },
 418 #ifdef CONFIG_MPC83XX_TSEC1
 419         {       "/" OF_SOC "/ethernet@24000,
 420                 "mac-address",
 421                 fdt_set_eth0
 422         },
 423         {       "/" OF_SOC "/ethernet@24000,
 424                 "local-mac-address",
 425                 fdt_set_eth0
 426         },
 427 #endif
 428 #ifdef CONFIG_MPC83XX_TSEC2
 429         {       "/" OF_SOC "/ethernet@25000,
 430                 "mac-address",
 431                 fdt_set_eth1
 432         },
 433         {       "/" OF_SOC "/ethernet@25000,
 434                 "local-mac-address",
 435                 fdt_set_eth1
 436         },
 437 #endif
 438 #ifdef CONFIG_UEC_ETH1
 439 #if CFG_UEC1_UCC_NUM == 0  /* UCC1 */
 440         {       "/" OF_QE "/ucc@2000/mac-address",
 441                 "mac-address",
 442                 fdt_set_eth0
 443         },
 444         {       "/" OF_QE "/ucc@2000/mac-address",
 445                 "local-mac-address",
 446                 fdt_set_eth0
 447         },
 448 #elif CFG_UEC1_UCC_NUM == 2  /* UCC3 */
 449         {       "/" OF_QE "/ucc@2200/mac-address",
 450                 "mac-address",
 451                 fdt_set_eth0
 452         },
 453         {       "/" OF_QE "/ucc@2200/mac-address",
 454                 "local-mac-address",
 455                 fdt_set_eth0
 456         },
 457 #endif
 458 #endif
 459 #ifdef CONFIG_UEC_ETH2
 460 #if CFG_UEC2_UCC_NUM == 1  /* UCC2 */
 461         {       "/" OF_QE "/ucc@3000/mac-address",
 462                 "mac-address",
 463                 fdt_set_eth1
 464         },
 465         {       "/" OF_QE "/ucc@3000/mac-address",
 466                 "local-mac-address",
 467                 fdt_set_eth1
 468         },
 469 #elif CFG_UEC1_UCC_NUM == 3  /* UCC4 */
 470         {       "/" OF_QE "/ucc@3200/mac-address",
 471                 "mac-address",
 472                 fdt_set_eth1
 473         },
 474         {       "/" OF_QE "/ucc@3200/mac-address",
 475                 "local-mac-address",
 476                 fdt_set_eth1
 477         },
 478 #endif
 479 #endif
 480 };
 481
 482 void
 483 ft_cpu_setup(void *blob, bd_t *bd)
 484 {
 485         int  nodeoffset;
 486         int  err;
 487         int  j;
 488
 489         for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) {
 490                 nodeoffset = fdt_path_offset(fdt, fixup_props[j].node);
 491                 if (nodeoffset >= 0) {
 492                         err = (*fixup_props[j].set_fn)(blob, nodeoffset, fixup_props[j].prop, bd);
 493                         if (err < 0)
 494                                 printf("set_fn/libfdt: %s %s returned %s\n",
 495                                         fixup_props[j].node,
 496                                         fixup_props[j].prop,
 497                                         fdt_strerror(err));
 498                 }
 499         }
 500 }
 501 #endif
 502
 503 #if defined(CONFIG_OF_FLAT_TREE)
 504 void
 505 ft_cpu_setup(void *blob, bd_t *bd)
 506 {
 507         u32 *p;
 508         int len;
 509         ulong clock;
 510
 511         clock = bd->bi_busfreq;
 512         p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
 513         if (p != NULL)
 514                 *p = cpu_to_be32(clock);
 515
 516         p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
 517         if (p != NULL)
 518                 *p = cpu_to_be32(clock);
 519
 520         p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
 521         if (p != NULL)
 522                 *p = cpu_to_be32(clock);
 523
 524         p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
 525         if (p != NULL)
 526                 *p = cpu_to_be32(clock);
 527
 528 #ifdef CONFIG_MPC83XX_TSEC1
 529         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
 530         if (p != NULL)
 531                 memcpy(p, bd->bi_enetaddr, 6);
 532
 533         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
 534         if (p != NULL)
 535                 memcpy(p, bd->bi_enetaddr, 6);
 536 #endif
 537
 538 #ifdef CONFIG_MPC83XX_TSEC2
 539         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
 540         if (p != NULL)
 541                 memcpy(p, bd->bi_enet1addr, 6);
 542
 543         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
 544         if (p != NULL)
 545                 memcpy(p, bd->bi_enet1addr, 6);
 546 #endif
 547
 548 #ifdef CONFIG_UEC_ETH1
 549 #if CFG_UEC1_UCC_NUM == 0  /* UCC1 */
 550         p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
 551         if (p != NULL)
 552                 memcpy(p, bd->bi_enetaddr, 6);
 553
 554         p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
 555         if (p != NULL)
 556                 memcpy(p, bd->bi_enetaddr, 6);
 557 #elif CFG_UEC1_UCC_NUM == 2  /* UCC3 */
 558         p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/mac-address", &len);
 559         if (p != NULL)
 560                 memcpy(p, bd->bi_enetaddr, 6);
 561
 562         p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/local-mac-address", &len);
 563         if (p != NULL)
 564                 memcpy(p, bd->bi_enetaddr, 6);
 565 #endif
 566 #endif
 567
 568 #ifdef CONFIG_UEC_ETH2
 569 #if CFG_UEC2_UCC_NUM == 1  /* UCC2 */
 570         p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
 571         if (p != NULL)
 572                 memcpy(p, bd->bi_enet1addr, 6);
 573
 574         p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
 575         if (p != NULL)
 576                 memcpy(p, bd->bi_enet1addr, 6);
 577 #elif CFG_UEC2_UCC_NUM == 3  /* UCC4 */
 578         p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/mac-address", &len);
 579         if (p != NULL)
 580                 memcpy(p, bd->bi_enet1addr, 6);
 581
 582         p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/local-mac-address", &len);
 583         if (p != NULL)
 584                 memcpy(p, bd->bi_enet1addr, 6);
 585 #endif
 586 #endif
 587 }
 588 #endif
 589
 590 #if defined(CONFIG_DDR_ECC)
 591 void dma_init(void)
 592 {
 593         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 594         volatile dma83xx_t *dma = &immap->dma;
 595         volatile u32 status = swab32(dma->dmasr0);
 596         volatile u32 dmamr0 = swab32(dma->dmamr0);
 597
 598         debug("DMA-init\n");
 599
 600         /* initialize DMASARn, DMADAR and DMAABCRn */
 601         dma->dmadar0 = (u32)0;
 602         dma->dmasar0 = (u32)0;
 603         dma->dmabcr0 = 0;
 604
 605         __asm__ __volatile__ ("sync");
 606         __asm__ __volatile__ ("isync");
 607
 608         /* clear CS bit */
 609         dmamr0 &= ~DMA_CHANNEL_START;
 610         dma->dmamr0 = swab32(dmamr0);
 611         __asm__ __volatile__ ("sync");
 612         __asm__ __volatile__ ("isync");
 613
 614         /* while the channel is busy, spin */
 615         while(status & DMA_CHANNEL_BUSY) {
 616                 status = swab32(dma->dmasr0);
 617         }
 618
 619         debug("DMA-init end\n");
 620 }
 621
 622 uint dma_check(void)
 623 {
 624         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 625         volatile dma83xx_t *dma = &immap->dma;
 626         volatile u32 status = swab32(dma->dmasr0);
 627         volatile u32 byte_count = swab32(dma->dmabcr0);
 628
 629         /* while the channel is busy, spin */
 630         while (status & DMA_CHANNEL_BUSY) {
 631                 status = swab32(dma->dmasr0);
 632         }
 633
 634         if (status & DMA_CHANNEL_TRANSFER_ERROR) {
 635                 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
 636         }
 637
 638         return status;
 639 }
 640
 641 int dma_xfer(void *dest, u32 count, void *src)
 642 {
 643         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 644         volatile dma83xx_t *dma = &immap->dma;
 645         volatile u32 dmamr0;
 646
 647         /* initialize DMASARn, DMADAR and DMAABCRn */
 648         dma->dmadar0 = swab32((u32)dest);
 649         dma->dmasar0 = swab32((u32)src);
 650         dma->dmabcr0 = swab32(count);
 651
 652         __asm__ __volatile__ ("sync");
 653         __asm__ __volatile__ ("isync");
 654
 655         /* init direct transfer, clear CS bit */
 656         dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
 657                         DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
 658                         DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
 659
 660         dma->dmamr0 = swab32(dmamr0);
 661
 662         __asm__ __volatile__ ("sync");
 663         __asm__ __volatile__ ("isync");
 664
 665         /* set CS to start DMA transfer */
 666         dmamr0 |= DMA_CHANNEL_START;
 667         dma->dmamr0 = swab32(dmamr0);
 668         __asm__ __volatile__ ("sync");
 669         __asm__ __volatile__ ("isync");
 670
 671         return ((int)dma_check());
 672 }
 673 #endif /*CONFIG_DDR_ECC*/