2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
33 #include <asm/processor.h>
34 #if defined(CONFIG_OF_FLAT_TREE)
36 #elif defined(CONFIG_OF_LIBFDT)
40 DECLARE_GLOBAL_DATA_PTR
;
44 volatile immap_t
*immr
;
45 ulong clock
= gd
->cpu_clk
;
50 immr
= (immap_t
*)CFG_IMMR
;
54 switch (pvr
& 0xffff0000) {
68 printf("Unknown core, ");
71 spridr
= immr
->sysconf
.spridr
;
83 case SPR_8347E_REV10_TBGA
:
84 case SPR_8347E_REV11_TBGA
:
85 case SPR_8347E_REV31_TBGA
:
86 case SPR_8347E_REV10_PBGA
:
87 case SPR_8347E_REV11_PBGA
:
88 case SPR_8347E_REV31_PBGA
:
91 case SPR_8347_REV10_TBGA
:
92 case SPR_8347_REV11_TBGA
:
93 case SPR_8347_REV31_TBGA
:
94 case SPR_8347_REV10_PBGA
:
95 case SPR_8347_REV11_PBGA
:
96 case SPR_8347_REV31_PBGA
:
100 case SPR_8343E_REV11
:
101 case SPR_8343E_REV31
:
109 case SPR_8360E_REV10
:
110 case SPR_8360E_REV11
:
111 case SPR_8360E_REV12
:
112 case SPR_8360E_REV20
:
113 case SPR_8360E_REV21
:
123 case SPR_8323E_REV10
:
124 case SPR_8323E_REV11
:
131 case SPR_8321E_REV10
:
132 case SPR_8321E_REV11
:
142 case SPR_8311E_REV10
:
148 case SPR_8313E_REV10
:
152 printf("Rev: Unknown revision number:%08x\n"
153 "Warning: Unsupported cpu revision!\n",spridr
);
157 #if defined(CONFIG_MPC834X)
158 /* Multiple revisons of 834x processors may have the same SPRIDR value.
159 * So use PVR to identify the revision number.
161 printf("Rev: %02x at %s MHz", PVR_MAJ(pvr
)<<4 | PVR_MIN(pvr
), strmhz(buf
, clock
));
163 printf("Rev: %02x at %s MHz", spridr
& 0x0000FFFF, strmhz(buf
, clock
));
165 printf(", CSB: %4d MHz\n", gd
->csb_clk
/ 1000000);
172 * Program a UPM with the code supplied in the table.
174 * The 'dummy' variable is used to increment the MAD. 'dummy' is
175 * supposed to be a pointer to the memory of the device being
176 * programmed by the UPM. The data in the MDR is written into
177 * memory and the MAD is incremented every time there's a read
178 * from 'dummy'. Unfortunately, the current prototype for this
179 * function doesn't allow for passing the address of this
180 * device, and changing the prototype will break a number lots
181 * of other code, so we need to use a round-about way of finding
182 * the value for 'dummy'.
184 * The value can be extracted from the base address bits of the
185 * Base Register (BR) associated with the specific UPM. To find
186 * that BR, we need to scan all 8 BRs until we find the one that
187 * has its MSEL bits matching the UPM we want. Once we know the
188 * right BR, we can extract the base address bits from it.
190 * The MxMR and the BR and OR of the chosen bank should all be
191 * configured before calling this function.
194 * upm: 0=UPMA, 1=UPMB, 2=UPMC
195 * table: Pointer to an array of values to program
196 * size: Number of elements in the array. Must be 64 or less.
198 void upmconfig (uint upm
, uint
*table
, uint size
)
200 #if defined(CONFIG_MPC834X)
201 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
202 volatile lbus83xx_t
*lbus
= &immap
->lbus
;
203 volatile uchar
*dummy
= NULL
;
204 const u32 msel
= (upm
+ 4) << BR_MSEL_SHIFT
; /* What the MSEL field in BRn should be */
205 volatile u32
*mxmr
= &lbus
->mamr
+ upm
; /* Pointer to mamr, mbmr, or mcmr */
208 /* Scan all the banks to determine the base address of the device */
209 for (i
= 0; i
< 8; i
++) {
210 if ((lbus
->bank
[i
].br
& BR_MSEL
) == msel
) {
211 dummy
= (uchar
*) (lbus
->bank
[i
].br
& BR_BA
);
217 printf("Error: %s() could not find matching BR\n", __FUNCTION__
);
221 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
222 *mxmr
= (*mxmr
& 0xCFFFFFC0) | 0x10000000;
224 for (i
= 0; i
< size
; i
++) {
225 lbus
->mdr
= table
[i
];
226 __asm__
__volatile__ ("sync");
227 *dummy
; /* Write the value to memory and increment MAD */
228 __asm__
__volatile__ ("sync");
231 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
234 printf("Error: %s() not defined for this configuration.\n", __FUNCTION__
);
241 do_reset (cmd_tbl_t
* cmdtp
, int flag
, int argc
, char *argv
[])
244 #ifndef MPC83xx_RESET
248 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
251 /* Interrupts and MMU off */
252 __asm__
__volatile__ ("mfmsr %0":"=r" (msr
):);
254 msr
&= ~( MSR_EE
| MSR_IR
| MSR_DR
);
255 __asm__
__volatile__ ("mtmsr %0"::"r" (msr
));
257 /* enable Reset Control Reg */
258 immap
->reset
.rpr
= 0x52535445;
259 __asm__
__volatile__ ("sync");
260 __asm__
__volatile__ ("isync");
262 /* confirm Reset Control Reg is enabled */
263 while(!((immap
->reset
.rcer
) & RCER_CRE
));
265 printf("Resetting the board.");
270 /* perform reset, only one bit */
271 immap
->reset
.rcr
= RCR_SWHR
;
273 #else /* ! MPC83xx_RESET */
275 immap
->reset
.rmr
= RMR_CSRE
; /* Checkstop Reset enable */
277 /* Interrupts and MMU off */
278 __asm__
__volatile__ ("mfmsr %0":"=r" (msr
):);
280 msr
&= ~(MSR_ME
| MSR_EE
| MSR_IR
| MSR_DR
);
281 __asm__
__volatile__ ("mtmsr %0"::"r" (msr
));
284 * Trying to execute the next instruction at a non-existing address
285 * should cause a machine check, resulting in reset
287 addr
= CFG_RESET_ADDRESS
;
289 printf("resetting the board.");
291 ((void (*)(void)) addr
) ();
292 #endif /* MPC83xx_RESET */
299 * Get timebase clock frequency (like cpu_clk in Hz)
302 unsigned long get_tbclk(void)
306 tbclk
= (gd
->bus_clk
+ 3L) / 4L;
312 #if defined(CONFIG_WATCHDOG)
313 void watchdog_reset (void)
315 int re_enable
= disable_interrupts();
317 /* Reset the 83xx watchdog */
318 volatile immap_t
*immr
= (immap_t
*) CFG_IMMR
;
319 immr
->wdt
.swsrr
= 0x556c;
320 immr
->wdt
.swsrr
= 0xaa39;
323 enable_interrupts ();
327 #if defined(CONFIG_OF_LIBFDT)
330 * "Setter" functions used to add/modify FDT entries.
332 static int fdt_set_eth0(void *blob
, int nodeoffset
, const char *name
, bd_t
*bd
)
334 /* Fix it up if it exists, don't create it if it doesn't exist */
335 if (fdt_get_property(blob
, nodeoffset
, name
, 0)) {
336 return fdt_setprop(blob
, nodeoffset
, name
, bd
->bi_enetaddr
, 6);
340 #ifdef CONFIG_HAS_ETH1
341 /* second onboard ethernet port */
342 static int fdt_set_eth1(void *blob
, int nodeoffset
, const char *name
, bd_t
*bd
)
344 /* Fix it up if it exists, don't create it if it doesn't exist */
345 if (fdt_get_property(blob
, nodeoffset
, name
, 0)) {
346 return fdt_setprop(blob
, nodeoffset
, name
, bd
->bi_enet1addr
, 6);
351 #ifdef CONFIG_HAS_ETH2
352 /* third onboard ethernet port */
353 static int fdt_set_eth2(void *blob
, int nodeoffset
, const char *name
, bd_t
*bd
)
355 /* Fix it up if it exists, don't create it if it doesn't exist */
356 if (fdt_get_property(blob
, nodeoffset
, name
, 0)) {
357 return fdt_setprop(blob
, nodeoffset
, name
, bd
->bi_enet2addr
, 6);
362 #ifdef CONFIG_HAS_ETH3
363 /* fourth onboard ethernet port */
364 static int fdt_set_eth3(void *blob
, int nodeoffset
, const char *name
, bd_t
*bd
)
366 /* Fix it up if it exists, don't create it if it doesn't exist */
367 if (fdt_get_property(blob
, nodeoffset
, name
, 0)) {
368 return fdt_setprop(blob
, nodeoffset
, name
, bd
->bi_enet3addr
, 6);
374 static int fdt_set_busfreq(void *blob
, int nodeoffset
, const char *name
, bd_t
*bd
)
377 /* Create or update the property */
378 tmp
= cpu_to_be32(bd
->bi_busfreq
);
379 return fdt_setprop(blob
, nodeoffset
, name
, &tmp
, sizeof(tmp
));
382 static int fdt_set_tbfreq(void *blob
, int nodeoffset
, const char *name
, bd_t
*bd
)
385 /* Create or update the property */
386 tmp
= cpu_to_be32(OF_TBCLK
);
387 return fdt_setprop(blob
, nodeoffset
, name
, &tmp
, sizeof(tmp
));
391 static int fdt_set_clockfreq(void *blob
, int nodeoffset
, const char *name
, bd_t
*bd
)
394 /* Create or update the property */
395 tmp
= cpu_to_be32(gd
->core_clk
);
396 return fdt_setprop(blob
, nodeoffset
, name
, &tmp
, sizeof(tmp
));
400 static int fdt_set_qe_busfreq(void *blob
, int nodeoffset
, const char *name
, bd_t
*bd
)
403 /* Create or update the property */
404 tmp
= cpu_to_be32(gd
->qe_clk
);
405 return fdt_setprop(blob
, nodeoffset
, name
, &tmp
, sizeof(tmp
));
408 static int fdt_set_qe_brgfreq(void *blob
, int nodeoffset
, const char *name
, bd_t
*bd
)
411 /* Create or update the property */
412 tmp
= cpu_to_be32(gd
->brg_clk
);
413 return fdt_setprop(blob
, nodeoffset
, name
, &tmp
, sizeof(tmp
));
420 static const struct {
423 int (*set_fn
)(void *blob
, int nodeoffset
, const char *name
, bd_t
*bd
);
426 "timebase-frequency",
441 { "/" OF_SOC
"/serial@4500",
445 { "/" OF_SOC
"/serial@4600",
450 { "/" OF_SOC
"/ethernet@24000",
454 { "/" OF_SOC
"/ethernet@24000",
460 { "/" OF_SOC
"/ethernet@25000",
464 { "/" OF_SOC
"/ethernet@25000",
478 #ifdef CONFIG_UEC_ETH1
479 #if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
480 { "/" OF_QE
"/ucc@2000",
484 { "/" OF_QE
"/ucc@2000",
488 #elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
489 { "/" OF_QE
"/ucc@2200",
493 { "/" OF_QE
"/ucc@2200",
498 #endif /* CONFIG_UEC_ETH1 */
499 #ifdef CONFIG_UEC_ETH2
500 #if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
501 { "/" OF_QE
"/ucc@3000",
505 { "/" OF_QE
"/ucc@3000",
509 #elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */
510 { "/" OF_QE
"/ucc@3200",
514 { "/" OF_QE
"/ucc@3200",
519 #endif /* CONFIG_UEC_ETH2 */
520 #endif /* CONFIG_QE */
524 ft_cpu_setup(void *blob
, bd_t
*bd
)
530 for (j
= 0; j
< (sizeof(fixup_props
) / sizeof(fixup_props
[0])); j
++) {
531 nodeoffset
= fdt_find_node_by_path(blob
, fixup_props
[j
].node
);
532 if (nodeoffset
>= 0) {
533 err
= fixup_props
[j
].set_fn(blob
, nodeoffset
,
534 fixup_props
[j
].prop
, bd
);
536 debug("Problem setting %s = %s: %s\n",
541 debug("Couldn't find %s: %s\n",
543 fdt_strerror(nodeoffset
));
547 #elif defined(CONFIG_OF_FLAT_TREE)
549 ft_cpu_setup(void *blob
, bd_t
*bd
)
555 clock
= bd
->bi_busfreq
;
556 p
= ft_get_prop(blob
, "/cpus/" OF_CPU
"/bus-frequency", &len
);
558 *p
= cpu_to_be32(clock
);
560 p
= ft_get_prop(blob
, "/" OF_SOC
"/bus-frequency", &len
);
562 *p
= cpu_to_be32(clock
);
564 p
= ft_get_prop(blob
, "/" OF_SOC
"/serial@4500/clock-frequency", &len
);
566 *p
= cpu_to_be32(clock
);
568 p
= ft_get_prop(blob
, "/" OF_SOC
"/serial@4600/clock-frequency", &len
);
570 *p
= cpu_to_be32(clock
);
573 p
= ft_get_prop(blob
, "/" OF_SOC
"/ethernet@24000/mac-address", &len
);
575 memcpy(p
, bd
->bi_enetaddr
, 6);
577 p
= ft_get_prop(blob
, "/" OF_SOC
"/ethernet@24000/local-mac-address", &len
);
579 memcpy(p
, bd
->bi_enetaddr
, 6);
583 p
= ft_get_prop(blob
, "/" OF_SOC
"/ethernet@25000/mac-address", &len
);
585 memcpy(p
, bd
->bi_enet1addr
, 6);
587 p
= ft_get_prop(blob
, "/" OF_SOC
"/ethernet@25000/local-mac-address", &len
);
589 memcpy(p
, bd
->bi_enet1addr
, 6);
592 #ifdef CONFIG_UEC_ETH1
593 #if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
594 p
= ft_get_prop(blob
, "/" OF_QE
"/ucc@2000/mac-address", &len
);
596 memcpy(p
, bd
->bi_enetaddr
, 6);
598 p
= ft_get_prop(blob
, "/" OF_QE
"/ucc@2000/local-mac-address", &len
);
600 memcpy(p
, bd
->bi_enetaddr
, 6);
601 #elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
602 p
= ft_get_prop(blob
, "/" OF_QE
"/ucc@2200/mac-address", &len
);
604 memcpy(p
, bd
->bi_enetaddr
, 6);
606 p
= ft_get_prop(blob
, "/" OF_QE
"/ucc@2200/local-mac-address", &len
);
608 memcpy(p
, bd
->bi_enetaddr
, 6);
612 #ifdef CONFIG_UEC_ETH2
613 #if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
614 p
= ft_get_prop(blob
, "/" OF_QE
"/ucc@3000/mac-address", &len
);
616 memcpy(p
, bd
->bi_enet1addr
, 6);
618 p
= ft_get_prop(blob
, "/" OF_QE
"/ucc@3000/local-mac-address", &len
);
620 memcpy(p
, bd
->bi_enet1addr
, 6);
621 #elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */
622 p
= ft_get_prop(blob
, "/" OF_QE
"/ucc@3200/mac-address", &len
);
624 memcpy(p
, bd
->bi_enet1addr
, 6);
626 p
= ft_get_prop(blob
, "/" OF_QE
"/ucc@3200/local-mac-address", &len
);
628 memcpy(p
, bd
->bi_enet1addr
, 6);
634 #if defined(CONFIG_DDR_ECC)
637 volatile immap_t
*immap
= (immap_t
*)CFG_IMMR
;
638 volatile dma83xx_t
*dma
= &immap
->dma
;
639 volatile u32 status
= swab32(dma
->dmasr0
);
640 volatile u32 dmamr0
= swab32(dma
->dmamr0
);
644 /* initialize DMASARn, DMADAR and DMAABCRn */
645 dma
->dmadar0
= (u32
)0;
646 dma
->dmasar0
= (u32
)0;
649 __asm__
__volatile__ ("sync");
650 __asm__
__volatile__ ("isync");
653 dmamr0
&= ~DMA_CHANNEL_START
;
654 dma
->dmamr0
= swab32(dmamr0
);
655 __asm__
__volatile__ ("sync");
656 __asm__
__volatile__ ("isync");
658 /* while the channel is busy, spin */
659 while(status
& DMA_CHANNEL_BUSY
) {
660 status
= swab32(dma
->dmasr0
);
663 debug("DMA-init end\n");
668 volatile immap_t
*immap
= (immap_t
*)CFG_IMMR
;
669 volatile dma83xx_t
*dma
= &immap
->dma
;
670 volatile u32 status
= swab32(dma
->dmasr0
);
671 volatile u32 byte_count
= swab32(dma
->dmabcr0
);
673 /* while the channel is busy, spin */
674 while (status
& DMA_CHANNEL_BUSY
) {
675 status
= swab32(dma
->dmasr0
);
678 if (status
& DMA_CHANNEL_TRANSFER_ERROR
) {
679 printf ("DMA Error: status = %x @ %d\n", status
, byte_count
);
685 int dma_xfer(void *dest
, u32 count
, void *src
)
687 volatile immap_t
*immap
= (immap_t
*)CFG_IMMR
;
688 volatile dma83xx_t
*dma
= &immap
->dma
;
691 /* initialize DMASARn, DMADAR and DMAABCRn */
692 dma
->dmadar0
= swab32((u32
)dest
);
693 dma
->dmasar0
= swab32((u32
)src
);
694 dma
->dmabcr0
= swab32(count
);
696 __asm__
__volatile__ ("sync");
697 __asm__
__volatile__ ("isync");
699 /* init direct transfer, clear CS bit */
700 dmamr0
= (DMA_CHANNEL_TRANSFER_MODE_DIRECT
|
701 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B
|
702 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN
);
704 dma
->dmamr0
= swab32(dmamr0
);
706 __asm__
__volatile__ ("sync");
707 __asm__
__volatile__ ("isync");
709 /* set CS to start DMA transfer */
710 dmamr0
|= DMA_CHANNEL_START
;
711 dma
->dmamr0
= swab32(dmamr0
);
712 __asm__
__volatile__ ("sync");
713 __asm__
__volatile__ ("isync");
715 return ((int)dma_check());
717 #endif /*CONFIG_DDR_ECC*/