cpu/mpc83xx/cpu.c

   1 /*
   2  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * CPU specific code for the MPC83xx family.
  25  *
  26  * Derived from the MPC8260 and MPC85xx.
  27  */
  28
  29 #include <common.h>
  30 #include <watchdog.h>
  31 #include <command.h>
  32 #include <mpc83xx.h>
  33 #include <asm/processor.h>
  34 #include <libfdt.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 int checkcpu(void)
  39 {
  40         volatile immap_t *immr;
  41         ulong clock = gd->cpu_clk;
  42         u32 pvr = get_pvr();
  43         u32 spridr;
  44         char buf[32];
  45         int i;
  46
  47         const struct cpu_type {
  48                 char name[15];
  49                 u32 partid;
  50         } cpu_type_list [] = {
  51                 CPU_TYPE_ENTRY(8311),
  52                 CPU_TYPE_ENTRY(8313),
  53                 CPU_TYPE_ENTRY(8314),
  54                 CPU_TYPE_ENTRY(8315),
  55                 CPU_TYPE_ENTRY(8321),
  56                 CPU_TYPE_ENTRY(8323),
  57                 CPU_TYPE_ENTRY(8343),
  58                 CPU_TYPE_ENTRY(8347_TBGA_),
  59                 CPU_TYPE_ENTRY(8347_PBGA_),
  60                 CPU_TYPE_ENTRY(8349),
  61                 CPU_TYPE_ENTRY(8358_TBGA_),
  62                 CPU_TYPE_ENTRY(8358_PBGA_),
  63                 CPU_TYPE_ENTRY(8360),
  64                 CPU_TYPE_ENTRY(8377),
  65                 CPU_TYPE_ENTRY(8378),
  66                 CPU_TYPE_ENTRY(8379),
  67         };
  68
  69         immr = (immap_t *)CFG_IMMR;
  70
  71         puts("CPU:   ");
  72
  73         switch (pvr & 0xffff0000) {
  74                 case PVR_E300C1:
  75                         printf("e300c1, ");
  76                         break;
  77
  78                 case PVR_E300C2:
  79                         printf("e300c2, ");
  80                         break;
  81
  82                 case PVR_E300C3:
  83                         printf("e300c3, ");
  84                         break;
  85
  86                 case PVR_E300C4:
  87                         printf("e300c4, ");
  88                         break;
  89
  90                 default:
  91                         printf("Unknown core, ");
  92         }
  93
  94         spridr = immr->sysconf.spridr;
  95
  96         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
  97                 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
  98                         puts("MPC");
  99                         puts(cpu_type_list[i].name);
 100                         if (IS_E_PROCESSOR(spridr))
 101                                 puts("E");
 102                         if (REVID_MAJOR(spridr) >= 2)
 103                                 puts("A");
 104                         printf(", Rev: %d.%d", REVID_MAJOR(spridr),
 105                                REVID_MINOR(spridr));
 106                         break;
 107                 }
 108
 109         if (i == ARRAY_SIZE(cpu_type_list))
 110                 printf("(SPRIDR %08x unknown), ", spridr);
 111
 112         printf(" at %s MHz, ", strmhz(buf, clock));
 113
 114         printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
 115
 116         return 0;
 117 }
 118
 119
 120 /*
 121  * Program a UPM with the code supplied in the table.
 122  *
 123  * The 'dummy' variable is used to increment the MAD. 'dummy' is
 124  * supposed to be a pointer to the memory of the device being
 125  * programmed by the UPM.  The data in the MDR is written into
 126  * memory and the MAD is incremented every time there's a read
 127  * from 'dummy'. Unfortunately, the current prototype for this
 128  * function doesn't allow for passing the address of this
 129  * device, and changing the prototype will break a number lots
 130  * of other code, so we need to use a round-about way of finding
 131  * the value for 'dummy'.
 132  *
 133  * The value can be extracted from the base address bits of the
 134  * Base Register (BR) associated with the specific UPM.  To find
 135  * that BR, we need to scan all 8 BRs until we find the one that
 136  * has its MSEL bits matching the UPM we want.  Once we know the
 137  * right BR, we can extract the base address bits from it.
 138  *
 139  * The MxMR and the BR and OR of the chosen bank should all be
 140  * configured before calling this function.
 141  *
 142  * Parameters:
 143  * upm: 0=UPMA, 1=UPMB, 2=UPMC
 144  * table: Pointer to an array of values to program
 145  * size: Number of elements in the array.  Must be 64 or less.
 146  */
 147 void upmconfig (uint upm, uint *table, uint size)
 148 {
 149 #if defined(CONFIG_MPC834X)
 150         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 151         volatile lbus83xx_t *lbus = &immap->lbus;
 152         volatile uchar *dummy = NULL;
 153         const u32 msel = (upm + 4) << BR_MSEL_SHIFT;    /* What the MSEL field in BRn should be */
 154         volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
 155         uint i;
 156
 157         /* Scan all the banks to determine the base address of the device */
 158         for (i = 0; i < 8; i++) {
 159                 if ((lbus->bank[i].br & BR_MSEL) == msel) {
 160                         dummy = (uchar *) (lbus->bank[i].br & BR_BA);
 161                         break;
 162                 }
 163         }
 164
 165         if (!dummy) {
 166                 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
 167                 hang();
 168         }
 169
 170         /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
 171         *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
 172
 173         for (i = 0; i < size; i++) {
 174                 lbus->mdr = table[i];
 175                 __asm__ __volatile__ ("sync");
 176                 *dummy; /* Write the value to memory and increment MAD */
 177                 __asm__ __volatile__ ("sync");
 178         }
 179
 180         /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
 181         *mxmr &= 0xCFFFFFC0;
 182 #else
 183         printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
 184         hang();
 185 #endif
 186 }
 187
 188
 189 int
 190 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 191 {
 192         ulong msr;
 193 #ifndef MPC83xx_RESET
 194         ulong addr;
 195 #endif
 196
 197         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 198
 199 #ifdef MPC83xx_RESET
 200         /* Interrupts and MMU off */
 201         __asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
 202
 203         msr &= ~( MSR_EE | MSR_IR | MSR_DR);
 204         __asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
 205
 206         /* enable Reset Control Reg */
 207         immap->reset.rpr = 0x52535445;
 208         __asm__ __volatile__ ("sync");
 209         __asm__ __volatile__ ("isync");
 210
 211         /* confirm Reset Control Reg is enabled */
 212         while(!((immap->reset.rcer) & RCER_CRE));
 213
 214         printf("Resetting the board.");
 215         printf("\n");
 216
 217         udelay(200);
 218
 219         /* perform reset, only one bit */
 220         immap->reset.rcr = RCR_SWHR;
 221
 222 #else   /* ! MPC83xx_RESET */
 223
 224         immap->reset.rmr = RMR_CSRE;    /* Checkstop Reset enable */
 225
 226         /* Interrupts and MMU off */
 227         __asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
 228
 229         msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
 230         __asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
 231
 232         /*
 233          * Trying to execute the next instruction at a non-existing address
 234          * should cause a machine check, resulting in reset
 235          */
 236         addr = CFG_RESET_ADDRESS;
 237
 238         printf("resetting the board.");
 239         printf("\n");
 240         ((void (*)(void)) addr) ();
 241 #endif  /* MPC83xx_RESET */
 242
 243         return 1;
 244 }
 245
 246
 247 /*
 248  * Get timebase clock frequency (like cpu_clk in Hz)
 249  */
 250
 251 unsigned long get_tbclk(void)
 252 {
 253         ulong tbclk;
 254
 255         tbclk = (gd->bus_clk + 3L) / 4L;
 256
 257         return tbclk;
 258 }
 259
 260
 261 #if defined(CONFIG_WATCHDOG)
 262 void watchdog_reset (void)
 263 {
 264         int re_enable = disable_interrupts();
 265
 266         /* Reset the 83xx watchdog */
 267         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 268         immr->wdt.swsrr = 0x556c;
 269         immr->wdt.swsrr = 0xaa39;
 270
 271         if (re_enable)
 272                 enable_interrupts ();
 273 }
 274 #endif
 275
 276 #if defined(CONFIG_DDR_ECC)
 277 void dma_init(void)
 278 {
 279         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 280         volatile dma83xx_t *dma = &immap->dma;
 281         volatile u32 status = swab32(dma->dmasr0);
 282         volatile u32 dmamr0 = swab32(dma->dmamr0);
 283
 284         debug("DMA-init\n");
 285
 286         /* initialize DMASARn, DMADAR and DMAABCRn */
 287         dma->dmadar0 = (u32)0;
 288         dma->dmasar0 = (u32)0;
 289         dma->dmabcr0 = 0;
 290
 291         __asm__ __volatile__ ("sync");
 292         __asm__ __volatile__ ("isync");
 293
 294         /* clear CS bit */
 295         dmamr0 &= ~DMA_CHANNEL_START;
 296         dma->dmamr0 = swab32(dmamr0);
 297         __asm__ __volatile__ ("sync");
 298         __asm__ __volatile__ ("isync");
 299
 300         /* while the channel is busy, spin */
 301         while(status & DMA_CHANNEL_BUSY) {
 302                 status = swab32(dma->dmasr0);
 303         }
 304
 305         debug("DMA-init end\n");
 306 }
 307
 308 uint dma_check(void)
 309 {
 310         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 311         volatile dma83xx_t *dma = &immap->dma;
 312         volatile u32 status = swab32(dma->dmasr0);
 313         volatile u32 byte_count = swab32(dma->dmabcr0);
 314
 315         /* while the channel is busy, spin */
 316         while (status & DMA_CHANNEL_BUSY) {
 317                 status = swab32(dma->dmasr0);
 318         }
 319
 320         if (status & DMA_CHANNEL_TRANSFER_ERROR) {
 321                 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
 322         }
 323
 324         return status;
 325 }
 326
 327 int dma_xfer(void *dest, u32 count, void *src)
 328 {
 329         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 330         volatile dma83xx_t *dma = &immap->dma;
 331         volatile u32 dmamr0;
 332
 333         /* initialize DMASARn, DMADAR and DMAABCRn */
 334         dma->dmadar0 = swab32((u32)dest);
 335         dma->dmasar0 = swab32((u32)src);
 336         dma->dmabcr0 = swab32(count);
 337
 338         __asm__ __volatile__ ("sync");
 339         __asm__ __volatile__ ("isync");
 340
 341         /* init direct transfer, clear CS bit */
 342         dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
 343                         DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
 344                         DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
 345
 346         dma->dmamr0 = swab32(dmamr0);
 347
 348         __asm__ __volatile__ ("sync");
 349         __asm__ __volatile__ ("isync");
 350
 351         /* set CS to start DMA transfer */
 352         dmamr0 |= DMA_CHANNEL_START;
 353         dma->dmamr0 = swab32(dmamr0);
 354         __asm__ __volatile__ ("sync");
 355         __asm__ __volatile__ ("isync");
 356
 357         return ((int)dma_check());
 358 }
 359 #endif /*CONFIG_DDR_ECC*/