2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
33 #include <asm/processor.h>
34 #if defined(CONFIG_OF_FLAT_TREE)
37 #if defined(CONFIG_OF_LIBFDT)
39 #include <libfdt_env.h>
42 DECLARE_GLOBAL_DATA_PTR
;
47 volatile immap_t
*immr
;
48 ulong clock
= gd
->cpu_clk
;
53 immr
= (immap_t
*)CFG_IMMR
;
57 switch (pvr
& 0xffff0000) {
71 printf("Unknown core, ");
74 spridr
= immr
->sysconf
.spridr
;
86 case SPR_8347E_REV10_TBGA
:
87 case SPR_8347E_REV11_TBGA
:
88 case SPR_8347E_REV31_TBGA
:
89 case SPR_8347E_REV10_PBGA
:
90 case SPR_8347E_REV11_PBGA
:
91 case SPR_8347E_REV31_PBGA
:
94 case SPR_8347_REV10_TBGA
:
95 case SPR_8347_REV11_TBGA
:
96 case SPR_8347_REV31_TBGA
:
97 case SPR_8347_REV10_PBGA
:
98 case SPR_8347_REV11_PBGA
:
99 case SPR_8347_REV31_PBGA
:
102 case SPR_8343E_REV10
:
103 case SPR_8343E_REV11
:
104 case SPR_8343E_REV31
:
112 case SPR_8360E_REV10
:
113 case SPR_8360E_REV11
:
114 case SPR_8360E_REV12
:
115 case SPR_8360E_REV20
:
124 case SPR_8323E_REV10
:
125 case SPR_8323E_REV11
:
132 case SPR_8321E_REV10
:
133 case SPR_8321E_REV11
:
143 case SPR_8311E_REV10
:
149 case SPR_8313E_REV10
:
153 puts("Rev: Unknown revision number.\nWarning: Unsupported cpu revision!\n");
157 #if defined(CONFIG_MPC834X)
158 /* Multiple revisons of 834x processors may have the same SPRIDR value.
159 * So use PVR to identify the revision number.
161 printf("Rev: %02x at %s MHz", PVR_MAJ(pvr
)<<4 | PVR_MIN(pvr
), strmhz(buf
, clock
));
163 printf("Rev: %02x at %s MHz", spridr
& 0x0000FFFF, strmhz(buf
, clock
));
165 printf(", CSB: %4d MHz\n", gd
->csb_clk
/ 1000000);
172 * Program a UPM with the code supplied in the table.
174 * The 'dummy' variable is used to increment the MAD. 'dummy' is
175 * supposed to be a pointer to the memory of the device being
176 * programmed by the UPM. The data in the MDR is written into
177 * memory and the MAD is incremented every time there's a read
178 * from 'dummy'. Unfortunately, the current prototype for this
179 * function doesn't allow for passing the address of this
180 * device, and changing the prototype will break a number lots
181 * of other code, so we need to use a round-about way of finding
182 * the value for 'dummy'.
184 * The value can be extracted from the base address bits of the
185 * Base Register (BR) associated with the specific UPM. To find
186 * that BR, we need to scan all 8 BRs until we find the one that
187 * has its MSEL bits matching the UPM we want. Once we know the
188 * right BR, we can extract the base address bits from it.
190 * The MxMR and the BR and OR of the chosen bank should all be
191 * configured before calling this function.
194 * upm: 0=UPMA, 1=UPMB, 2=UPMC
195 * table: Pointer to an array of values to program
196 * size: Number of elements in the array. Must be 64 or less.
198 void upmconfig (uint upm
, uint
*table
, uint size
)
200 #if defined(CONFIG_MPC834X)
201 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
202 volatile lbus83xx_t
*lbus
= &immap
->lbus
;
203 volatile uchar
*dummy
= NULL
;
204 const u32 msel
= (upm
+ 4) << BR_MSEL_SHIFT
; /* What the MSEL field in BRn should be */
205 volatile u32
*mxmr
= &lbus
->mamr
+ upm
; /* Pointer to mamr, mbmr, or mcmr */
208 /* Scan all the banks to determine the base address of the device */
209 for (i
= 0; i
< 8; i
++) {
210 if ((lbus
->bank
[i
].br
& BR_MSEL
) == msel
) {
211 dummy
= (uchar
*) (lbus
->bank
[i
].br
& BR_BA
);
217 printf("Error: %s() could not find matching BR\n", __FUNCTION__
);
221 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
222 *mxmr
= (*mxmr
& 0xCFFFFFC0) | 0x10000000;
224 for (i
= 0; i
< size
; i
++) {
225 lbus
->mdr
= table
[i
];
226 __asm__
__volatile__ ("sync");
227 *dummy
; /* Write the value to memory and increment MAD */
228 __asm__
__volatile__ ("sync");
231 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
234 printf("Error: %s() not defined for this configuration.\n", __FUNCTION__
);
241 do_reset (cmd_tbl_t
* cmdtp
, int flag
, int argc
, char *argv
[])
244 #ifndef MPC83xx_RESET
248 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
251 /* Interrupts and MMU off */
252 __asm__
__volatile__ ("mfmsr %0":"=r" (msr
):);
254 msr
&= ~( MSR_EE
| MSR_IR
| MSR_DR
);
255 __asm__
__volatile__ ("mtmsr %0"::"r" (msr
));
257 /* enable Reset Control Reg */
258 immap
->reset
.rpr
= 0x52535445;
259 __asm__
__volatile__ ("sync");
260 __asm__
__volatile__ ("isync");
262 /* confirm Reset Control Reg is enabled */
263 while(!((immap
->reset
.rcer
) & RCER_CRE
));
265 printf("Resetting the board.");
270 /* perform reset, only one bit */
271 immap
->reset
.rcr
= RCR_SWHR
;
273 #else /* ! MPC83xx_RESET */
275 immap
->reset
.rmr
= RMR_CSRE
; /* Checkstop Reset enable */
277 /* Interrupts and MMU off */
278 __asm__
__volatile__ ("mfmsr %0":"=r" (msr
):);
280 msr
&= ~(MSR_ME
| MSR_EE
| MSR_IR
| MSR_DR
);
281 __asm__
__volatile__ ("mtmsr %0"::"r" (msr
));
284 * Trying to execute the next instruction at a non-existing address
285 * should cause a machine check, resulting in reset
287 addr
= CFG_RESET_ADDRESS
;
289 printf("resetting the board.");
291 ((void (*)(void)) addr
) ();
292 #endif /* MPC83xx_RESET */
299 * Get timebase clock frequency (like cpu_clk in Hz)
302 unsigned long get_tbclk(void)
306 tbclk
= (gd
->bus_clk
+ 3L) / 4L;
312 #if defined(CONFIG_WATCHDOG)
313 void watchdog_reset (void)
315 int re_enable
= disable_interrupts();
317 /* Reset the 83xx watchdog */
318 volatile immap_t
*immr
= (immap_t
*) CFG_IMMR
;
319 immr
->wdt
.swsrr
= 0x556c;
320 immr
->wdt
.swsrr
= 0xaa39;
323 enable_interrupts ();
327 #if defined(CONFIG_OF_LIBFDT)
330 * "Setter" functions used to add/modify FDT entries.
332 static int fdt_set_eth0(void *fdt
, int nodeoffset
, const char *name
, bd_t
*bd
)
335 * Fix it up if it exists, don't create it if it doesn't exist.
337 if (fdt_get_property(fdt
, nodeoffset
, name
, 0)) {
338 return fdt_setprop(fdt
, nodeoffset
, name
, bd
->bi_enetaddr
, 6);
340 return -FDT_ERR_NOTFOUND
;
342 #ifdef CONFIG_HAS_ETH1
343 /* second onboard ethernet port */
344 static int fdt_set_eth1(void *fdt
, int nodeoffset
, const char *name
, bd_t
*bd
)
347 * Fix it up if it exists, don't create it if it doesn't exist.
349 if (fdt_get_property(fdt
, nodeoffset
, name
, 0)) {
350 return fdt_setprop(fdt
, nodeoffset
, name
, bd
->bi_enet1addr
, 6);
352 return -FDT_ERR_NOTFOUND
;
355 #ifdef CONFIG_HAS_ETH2
356 /* third onboard ethernet port */
357 static int fdt_set_eth2(void *fdt
, int nodeoffset
, const char *name
, bd_t
*bd
)
360 * Fix it up if it exists, don't create it if it doesn't exist.
362 if (fdt_get_property(fdt
, nodeoffset
, name
, 0)) {
363 return fdt_setprop(fdt
, nodeoffset
, name
, bd
->bi_enet2addr
, 6);
365 return -FDT_ERR_NOTFOUND
;
368 #ifdef CONFIG_HAS_ETH3
369 /* fourth onboard ethernet port */
370 static int fdt_set_eth3(void *fdt
, int nodeoffset
, const char *name
, bd_t
*bd
)
373 * Fix it up if it exists, don't create it if it doesn't exist.
375 if (fdt_get_property(fdt
, nodeoffset
, name
, 0)) {
376 return fdt_setprop(fdt
, nodeoffset
, name
, bd
->bi_enet3addr
, 6);
378 return -FDT_ERR_NOTFOUND
;
382 static int fdt_set_busfreq(void *fdt
, int nodeoffset
, const char *name
, bd_t
*bd
)
386 * Create or update the property.
388 tmp
= cpu_to_be32(bd
->bi_busfreq
);
389 return fdt_setprop(fdt
, nodeoffset
, name
, &tmp
, sizeof(tmp
));
393 * Fixups to the fdt. If "create" is TRUE, the node is created
394 * unconditionally. If "create" is FALSE, the node is updated
395 * only if it already exists.
397 static const struct {
400 int (*set_fn
)(void *fdt
, int nodeoffset
, const char *name
, bd_t
*bd
);
410 { "/" OF_SOC
"/serial@4500/",
414 { "/" OF_SOC
"/serial@4600/",
419 { "/" OF_SOC
"/ethernet@24000,
423 { "/" OF_SOC "/ethernet@
24000,
429 { "/" OF_SOC
"/ethernet@25000,
433 { "/" OF_SOC "/ethernet@
25000,
438 #ifdef CONFIG_UEC_ETH1
439 #if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
440 { "/" OF_QE
"/ucc@2000/mac-address",
444 { "/" OF_QE
"/ucc@2000/mac-address",
448 #elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
449 { "/" OF_QE
"/ucc@2200/mac-address",
453 { "/" OF_QE
"/ucc@2200/mac-address",
459 #ifdef CONFIG_UEC_ETH2
460 #if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
461 { "/" OF_QE
"/ucc@3000/mac-address",
465 { "/" OF_QE
"/ucc@3000/mac-address",
469 #elif CFG_UEC1_UCC_NUM == 3 /* UCC4 */
470 { "/" OF_QE
"/ucc@3200/mac-address",
474 { "/" OF_QE
"/ucc@3200/mac-address",
483 ft_cpu_setup(void *blob
, bd_t
*bd
)
489 for (j
= 0; j
< (sizeof(fixup_props
) / sizeof(fixup_props
[0])); j
++) {
490 nodeoffset
= fdt_path_offset(fdt
, fixup_props
[j
].node
);
491 if (nodeoffset
>= 0) {
492 err
= (*fixup_props
[j
].set_fn
)(blob
, nodeoffset
, fixup_props
[j
].prop
, bd
);
494 printf("set_fn/libfdt: %s %s returned %s\n",
503 #if defined(CONFIG_OF_FLAT_TREE)
505 ft_cpu_setup(void *blob
, bd_t
*bd
)
511 clock
= bd
->bi_busfreq
;
512 p
= ft_get_prop(blob
, "/cpus/" OF_CPU
"/bus-frequency", &len
);
514 *p
= cpu_to_be32(clock
);
516 p
= ft_get_prop(blob
, "/" OF_SOC
"/bus-frequency", &len
);
518 *p
= cpu_to_be32(clock
);
520 p
= ft_get_prop(blob
, "/" OF_SOC
"/serial@4500/clock-frequency", &len
);
522 *p
= cpu_to_be32(clock
);
524 p
= ft_get_prop(blob
, "/" OF_SOC
"/serial@4600/clock-frequency", &len
);
526 *p
= cpu_to_be32(clock
);
529 p
= ft_get_prop(blob
, "/" OF_SOC
"/ethernet@24000/mac-address", &len
);
531 memcpy(p
, bd
->bi_enetaddr
, 6);
533 p
= ft_get_prop(blob
, "/" OF_SOC
"/ethernet@24000/local-mac-address", &len
);
535 memcpy(p
, bd
->bi_enetaddr
, 6);
539 p
= ft_get_prop(blob
, "/" OF_SOC
"/ethernet@25000/mac-address", &len
);
541 memcpy(p
, bd
->bi_enet1addr
, 6);
543 p
= ft_get_prop(blob
, "/" OF_SOC
"/ethernet@25000/local-mac-address", &len
);
545 memcpy(p
, bd
->bi_enet1addr
, 6);
548 #ifdef CONFIG_UEC_ETH1
549 #if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
550 p
= ft_get_prop(blob
, "/" OF_QE
"/ucc@2000/mac-address", &len
);
552 memcpy(p
, bd
->bi_enetaddr
, 6);
554 p
= ft_get_prop(blob
, "/" OF_QE
"/ucc@2000/local-mac-address", &len
);
556 memcpy(p
, bd
->bi_enetaddr
, 6);
557 #elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
558 p
= ft_get_prop(blob
, "/" OF_QE
"/ucc@2200/mac-address", &len
);
560 memcpy(p
, bd
->bi_enetaddr
, 6);
562 p
= ft_get_prop(blob
, "/" OF_QE
"/ucc@2200/local-mac-address", &len
);
564 memcpy(p
, bd
->bi_enetaddr
, 6);
568 #ifdef CONFIG_UEC_ETH2
569 #if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
570 p
= ft_get_prop(blob
, "/" OF_QE
"/ucc@3000/mac-address", &len
);
572 memcpy(p
, bd
->bi_enet1addr
, 6);
574 p
= ft_get_prop(blob
, "/" OF_QE
"/ucc@3000/local-mac-address", &len
);
576 memcpy(p
, bd
->bi_enet1addr
, 6);
577 #elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */
578 p
= ft_get_prop(blob
, "/" OF_QE
"/ucc@3200/mac-address", &len
);
580 memcpy(p
, bd
->bi_enet1addr
, 6);
582 p
= ft_get_prop(blob
, "/" OF_QE
"/ucc@3200/local-mac-address", &len
);
584 memcpy(p
, bd
->bi_enet1addr
, 6);
590 #if defined(CONFIG_DDR_ECC)
593 volatile immap_t
*immap
= (immap_t
*)CFG_IMMR
;
594 volatile dma83xx_t
*dma
= &immap
->dma
;
595 volatile u32 status
= swab32(dma
->dmasr0
);
596 volatile u32 dmamr0
= swab32(dma
->dmamr0
);
600 /* initialize DMASARn, DMADAR and DMAABCRn */
601 dma
->dmadar0
= (u32
)0;
602 dma
->dmasar0
= (u32
)0;
605 __asm__
__volatile__ ("sync");
606 __asm__
__volatile__ ("isync");
609 dmamr0
&= ~DMA_CHANNEL_START
;
610 dma
->dmamr0
= swab32(dmamr0
);
611 __asm__
__volatile__ ("sync");
612 __asm__
__volatile__ ("isync");
614 /* while the channel is busy, spin */
615 while(status
& DMA_CHANNEL_BUSY
) {
616 status
= swab32(dma
->dmasr0
);
619 debug("DMA-init end\n");
624 volatile immap_t
*immap
= (immap_t
*)CFG_IMMR
;
625 volatile dma83xx_t
*dma
= &immap
->dma
;
626 volatile u32 status
= swab32(dma
->dmasr0
);
627 volatile u32 byte_count
= swab32(dma
->dmabcr0
);
629 /* while the channel is busy, spin */
630 while (status
& DMA_CHANNEL_BUSY
) {
631 status
= swab32(dma
->dmasr0
);
634 if (status
& DMA_CHANNEL_TRANSFER_ERROR
) {
635 printf ("DMA Error: status = %x @ %d\n", status
, byte_count
);
641 int dma_xfer(void *dest
, u32 count
, void *src
)
643 volatile immap_t
*immap
= (immap_t
*)CFG_IMMR
;
644 volatile dma83xx_t
*dma
= &immap
->dma
;
647 /* initialize DMASARn, DMADAR and DMAABCRn */
648 dma
->dmadar0
= swab32((u32
)dest
);
649 dma
->dmasar0
= swab32((u32
)src
);
650 dma
->dmabcr0
= swab32(count
);
652 __asm__
__volatile__ ("sync");
653 __asm__
__volatile__ ("isync");
655 /* init direct transfer, clear CS bit */
656 dmamr0
= (DMA_CHANNEL_TRANSFER_MODE_DIRECT
|
657 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B
|
658 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN
);
660 dma
->dmamr0
= swab32(dmamr0
);
662 __asm__
__volatile__ ("sync");
663 __asm__
__volatile__ ("isync");
665 /* set CS to start DMA transfer */
666 dmamr0
|= DMA_CHANNEL_START
;
667 dma
->dmamr0
= swab32(dmamr0
);
668 __asm__
__volatile__ ("sync");
669 __asm__
__volatile__ ("isync");
671 return ((int)dma_check());
673 #endif /*CONFIG_DDR_ECC*/