cpu/mpc83xx/pci.c

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2007
   3  *
   4  * Author: Scott Wood <scottwood@freescale.com>,
   5  * with some bits from older board-specific PCI initialization.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <pci.h>
  28 #include <asm/mpc8349_pci.h>
  29
  30 #ifdef CONFIG_83XX_GENERIC_PCI
  31 #define MAX_BUSES 2
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 static struct pci_controller pci_hose[MAX_BUSES];
  36 static int pci_num_buses;
  37
  38 static void pci_init_bus(int bus, struct pci_region *reg)
  39 {
  40         volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
  41         volatile pot83xx_t *pot = immr->ios.pot;
  42         volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
  43         struct pci_controller *hose = &pci_hose[bus];
  44         u32 dev;
  45         u16 reg16;
  46         int i;
  47
  48         if (bus == 1)
  49                 pot += 3;
  50
  51         /* Setup outbound translation windows */
  52         for (i = 0; i < 3; i++, reg++, pot++) {
  53                 if (reg->size == 0)
  54                         break;
  55
  56                 hose->regions[i] = *reg;
  57                 hose->region_count++;
  58
  59                 pot->potar = reg->bus_start >> 12;
  60                 pot->pobar = reg->phys_start >> 12;
  61                 pot->pocmr = ~(reg->size - 1) >> 12;
  62
  63                 if (reg->flags & PCI_REGION_IO)
  64                         pot->pocmr |= POCMR_IO;
  65 #ifdef CONFIG_83XX_PCI_STREAMING
  66                 else if (reg->flags & PCI_REGION_PREFETCH)
  67                         pot->pocmr |= POCMR_SE;
  68 #endif
  69
  70                 if (bus == 1)
  71                         pot->pocmr |= POCMR_DST;
  72
  73                 pot->pocmr |= POCMR_EN;
  74         }
  75
  76         /* Point inbound translation at RAM */
  77         pci_ctrl->pitar1 = 0;
  78         pci_ctrl->pibar1 = 0;
  79         pci_ctrl->piebar1 = 0;
  80         pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
  81                            PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
  82
  83         i = hose->region_count++;
  84         hose->regions[i].bus_start = 0;
  85         hose->regions[i].phys_start = 0;
  86         hose->regions[i].size = gd->ram_size;
  87         hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
  88
  89         hose->first_busno = 0;
  90         hose->last_busno = 0xff;
  91
  92         pci_setup_indirect(hose, CFG_IMMR + 0x8300 + bus * 0x80,
  93                                  CFG_IMMR + 0x8304 + bus * 0x80);
  94
  95         pci_register_hose(hose);
  96
  97         /*
  98          * Write to Command register
  99          */
 100         reg16 = 0xff;
 101         dev = PCI_BDF(hose->first_busno, 0, 0);
 102         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
 103         reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 104         pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
 105
 106         /*
 107          * Clear non-reserved bits in status register.
 108          */
 109         pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
 110         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 111         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 112
 113 #ifdef CONFIG_PCI_SCAN_SHOW
 114         printf("PCI:   Bus Dev VenId DevId Class Int\n");
 115 #endif
 116         /*
 117          * Hose scan.
 118          */
 119         hose->last_busno = pci_hose_scan(hose);
 120 }
 121
 122 /*
 123  * The caller must have already set OCCR, and the PCI_LAW BARs
 124  * must have been set to cover all of the requested regions.
 125  *
 126  * If fewer than three regions are requested, then the region
 127  * list is terminated with a region of size 0.
 128  */
 129 void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
 130 {
 131         volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
 132         int i;
 133
 134         if (num_buses > MAX_BUSES) {
 135                 printf("%d PCI buses requsted, %d supported\n",
 136                        num_buses, MAX_BUSES);
 137
 138                 num_buses = MAX_BUSES;
 139         }
 140
 141         pci_num_buses = num_buses;
 142
 143         /*
 144          * Release PCI RST Output signal.
 145          * Power on to RST high must be at least 100 ms as per PCI spec.
 146          * On warm boots only 1 ms is required.
 147          */
 148         udelay(warmboot ? 1000 : 100000);
 149
 150         for (i = 0; i < num_buses; i++)
 151                 immr->pci_ctrl[i].gcr = 1;
 152
 153         /*
 154          * RST high to first config access must be at least 2^25 cycles
 155          * as per PCI spec.  This could be cut in half if we know we're
 156          * running at 66MHz.  This could be insufficiently long if we're
 157          * running the PCI bus at significantly less than 33MHz.
 158          */
 159         udelay(1020000);
 160
 161         for (i = 0; i < num_buses; i++)
 162                 pci_init_bus(i, reg[i]);
 163 }
 164
 165 #ifdef CONFIG_OF_FLAT_TREE
 166 void ft_pci_setup(void *blob, bd_t *bd)
 167 {
 168         u32 *p;
 169         int len;
 170
 171         if (pci_num_buses < 1)
 172                 return;
 173
 174         p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
 175         if (p) {
 176                 p[0] = pci_hose[0].first_busno;
 177                 p[1] = pci_hose[0].last_busno;
 178         }
 179
 180         if (pci_num_buses < 2)
 181                 return;
 182
 183         p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
 184         if (p) {
 185                 p[0] = pci_hose[1].first_busno;
 186                 p[1] = pci_hose[1].last_busno;
 187         }
 188 }
 189 #endif /* CONFIG_OF_FLAT_TREE */
 190
 191 #endif /* CONFIG_83XX_GENERIC_PCI */