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git.ipfire.org Git - people/ms/u-boot.git/blob - cpu/mpc83xx/spd_sdram.c
2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * 20050101: Eran Liberty (liberty@freescale.com)
27 * Initial file creating (porting from 85XX & 8260)
31 #include <asm/processor.h>
35 #include <spd_sdram.h>
37 #ifdef CONFIG_SPD_EEPROM
39 #if defined(CONFIG_DDR_ECC)
40 extern void dma_init(void);
41 extern uint
dma_check(void);
42 extern int dma_xfer(void *dest
, uint count
, void *src
);
46 #define CFG_READ_SPD i2c_read
50 * Convert picoseconds into clock cycles (rounding up if needed).
54 picos_to_clk(int picos
)
58 clks
= picos
/ (2000000000 / (get_bus_freq(0) / 1000));
59 if (picos
% (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
67 banksize(unsigned char row_dens
)
69 return ((row_dens
>> 2) | ((row_dens
& 3) << 6)) << 24;
72 long int spd_sdram(int(read_spd
)(uint addr
))
74 volatile immap_t
*immap
= (immap_t
*)CFG_IMMRBAR
;
75 volatile ddr8349_t
*ddr
= &immap
->ddr
;
76 volatile law8349_t
*ecm
= &immap
->sysconf
.ddrlaw
[0];
80 unsigned int law_size
;
82 unsigned int trfc
, trfc_clk
, trfc_low
;
84 #warning Current spd_sdram does not fit its usage... adjust implementation or API...
86 CFG_READ_SPD(SPD_EEPROM_ADDRESS
, 0, 1, (uchar
*) & spd
, sizeof (spd
));
89 puts("DDR:Only two chip selects are supported on ADS.\n");
93 if (spd
.nrow_addr
< 12
96 || spd
.ncol_addr
> 11) {
97 puts("DDR:Row or Col number unsupported.\n");
101 ddr
->csbnds
[2].csbnds
= (banksize(spd
.row_dens
) >> 24) - 1;
102 ddr
->cs_config
[2] = ( 1 << 31
103 | (spd
.nrow_addr
- 12) << 8
104 | (spd
.ncol_addr
- 8) );
106 debug("cs2_bnds = 0x%08x\n",ddr
->csbnds
[2].csbnds
);
107 debug("cs2_config = 0x%08x\n",ddr
->cs_config
[2]);
109 if (spd
.nrows
== 2) {
110 ddr
->csbnds
[3].csbnds
= ( (banksize(spd
.row_dens
) >> 8)
111 | ((banksize(spd
.row_dens
) >> 23) - 1) );
112 ddr
->cs_config
[3] = ( 1<<31
113 | (spd
.nrow_addr
-12) << 8
114 | (spd
.ncol_addr
-8) );
115 debug("cs3_bnds = 0x%08x\n",ddr
->csbnds
[3].csbnds
);
116 debug("cs3_config = 0x%08x\n",ddr
->cs_config
[3]);
119 if (spd
.mem_type
!= 0x07) {
120 puts("No DDR module found!\n");
125 * Figure out memory size in Megabytes.
127 memsize
= spd
.nrows
* banksize(spd
.row_dens
) / 0x100000;
130 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
132 law_size
= 19 + __ilog2(memsize
);
135 * Set up LAWBAR for all of DDR.
137 ecm
->bar
= ((CFG_DDR_SDRAM_BASE
>>12) & 0xfffff);
138 ecm
->ar
= (LAWAR_EN
| LAWAR_TRGT_IF_DDR
| (LAWAR_SIZE
& law_size
));
139 debug("DDR:bar=0x%08x\n", ecm
->bar
);
140 debug("DDR:ar=0x%08x\n", ecm
->ar
);
143 * find the largest CAS
145 if(spd
.cas_lat
& 0x40) {
147 } else if (spd
.cas_lat
& 0x20) {
149 } else if (spd
.cas_lat
& 0x10) {
151 } else if (spd
.cas_lat
& 0x08) {
153 } else if (spd
.cas_lat
& 0x04) {
155 } else if (spd
.cas_lat
& 0x02) {
157 } else if (spd
.cas_lat
& 0x01) {
160 puts("DDR:no valid CAS Latency information.\n");
164 tmp
= 20000 / (((spd
.clk_cycle
& 0xF0) >> 4) * 10
165 + (spd
.clk_cycle
& 0x0f));
166 debug("DDR:Module maximum data rate is: %dMhz\n", tmp
);
168 tmp1
= get_bus_freq(0) / 1000000;
169 if (tmp1
< 230 && tmp1
>= 90 && tmp
>= 230) {
170 /* 90~230 range, treated as DDR 200 */
171 if (spd
.clk_cycle3
== 0xa0)
173 else if(spd
.clk_cycle2
== 0xa0)
175 } else if (tmp1
< 280 && tmp1
>= 230 && tmp
>= 280) {
176 /* 230-280 range, treated as DDR 266 */
177 if (spd
.clk_cycle3
== 0x75)
179 else if (spd
.clk_cycle2
== 0x75)
181 } else if (tmp1
< 350 && tmp1
>= 280 && tmp
>= 350) {
182 /* 280~350 range, treated as DDR 333 */
183 if (spd
.clk_cycle3
== 0x60)
185 else if (spd
.clk_cycle2
== 0x60)
187 } else if (tmp1
< 90 || tmp1
>= 350) {
188 /* DDR rate out-of-range */
189 puts("DDR:platform frequency is not fit for DDR rate\n");
194 * note: caslat must also be programmed into ddr->sdram_mode
197 * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
198 * use conservative value here.
200 trfc
= spd
.trfc
* 1000; /* up to ps */
201 trfc_clk
= picos_to_clk(trfc
);
202 trfc_low
= (trfc_clk
- 8) & 0xf;
205 (((picos_to_clk(spd
.trp
* 250) & 0x07) << 28 ) |
206 ((picos_to_clk(spd
.tras
* 1000) & 0x0f ) << 24 ) |
207 ((picos_to_clk(spd
.trcd
* 250) & 0x07) << 20 ) |
208 ((caslat
& 0x07) << 16 ) |
211 ((picos_to_clk(spd
.trrd
* 250) & 0x07) << 4) | 1);
213 ddr
->timing_cfg_2
= 0x00000800;
215 debug("DDR:timing_cfg_1=0x%08x\n", ddr
->timing_cfg_1
);
216 debug("DDR:timing_cfg_2=0x%08x\n", ddr
->timing_cfg_2
);
219 * Only DDR I is supported
220 * DDR I and II have different mode-register-set definition
223 /* burst length is always 4 */
226 ddr
->sdram_mode
= 0x52; /* 1.5 */
229 ddr
->sdram_mode
= 0x22; /* 2.0 */
232 ddr
->sdram_mode
= 0x62; /* 2.5 */
235 ddr
->sdram_mode
= 0x32; /* 3.0 */
238 puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
241 debug("DDR:sdram_mode=0x%08x\n", ddr
->sdram_mode
);
243 switch(spd
.refresh
) {
246 tmp
= picos_to_clk(15625000);
250 tmp
= picos_to_clk(3900000);
254 tmp
= picos_to_clk(7800000);
258 tmp
= picos_to_clk(31300000);
262 tmp
= picos_to_clk(62500000);
266 tmp
= picos_to_clk(125000000);
274 * Set BSTOPRE to 0x100 for page mode
275 * If auto-charge is used, set BSTOPRE = 0
277 ddr
->sdram_interval
= ((tmp
& 0x3fff) << 16) | 0x100;
278 debug("DDR:sdram_interval=0x%08x\n", ddr
->sdram_interval
);
281 * Is this an ECC DDR chip?
283 #if defined(CONFIG_DDR_ECC)
284 if (spd
.config
== 0x02) {
285 ddr
->err_disable
= 0x0000000d;
286 ddr
->err_sbe
= 0x00ff0000;
288 debug("DDR:err_disable=0x%08x\n", ddr
->err_disable
);
289 debug("DDR:err_sbe=0x%08x\n", ddr
->err_sbe
);
297 * CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
298 * clock cycle after address/command
300 ddr
->sdram_clk_cntl
= 0x82000000;
303 * Figure out the settings for the sdram_cfg register. Build up
304 * the entire register in 'tmp' before writing since the write into
305 * the register will actually enable the memory controller, and all
306 * settings must be done before enabling.
308 * sdram_cfg[0] = 1 (ddr sdram logic enable)
309 * sdram_cfg[1] = 1 (self-refresh-enable)
310 * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
315 * sdram_cfg[3] = RD_EN - registered DIMM enable
316 * A value of 0x26 indicates micron registered DIMMS (micron.com)
318 if (spd
.mod_attr
== 0x26) {
322 #if defined(CONFIG_DDR_ECC)
324 * If the user wanted ECC (enabled via sdram_cfg[2])
326 if (spd
.config
== 0x02) {
331 #if defined(CONFIG_DDR_2T_TIMING)
333 * Enable 2T timing by setting sdram_cfg[16].
335 tmp
|= SDRAM_CFG_2T_EN
;
338 ddr
->sdram_cfg
= tmp
;
342 debug("DDR:sdram_cfg=0x%08x\n", ddr
->sdram_cfg
);
344 return memsize
;/*in MBytes*/
346 #endif /* CONFIG_SPD_EEPROM */
349 #if defined(CONFIG_DDR_ECC)
351 * Initialize all of memory for ECC, then enable errors.
355 ddr_enable_ecc(unsigned int dram_size
)
360 volatile immap_t
*immap
= (immap_t
*)CFG_IMMRBAR
;
361 volatile ccsr_ddr_t
*ddr
= &immap
->im_ddr
;
365 for (*p
= 0; p
< (uint
*)(8 * 1024); p
++) {
366 if (((unsigned int)p
& 0x1f) == 0) {
367 ppcDcbz((unsigned long) p
);
369 *p
= (unsigned int)0xdeadbeef;
370 if (((unsigned int)p
& 0x1c) == 0x1c) {
371 ppcDcbf((unsigned long) p
);
376 dma_xfer((uint
*)0x2000, 0x2000, (uint
*)0);
378 dma_xfer((uint
*)0x4000, 0x4000, (uint
*)0);
380 dma_xfer((uint
*)0x8000, 0x8000, (uint
*)0);
382 dma_xfer((uint
*)0x10000, 0x10000, (uint
*)0);
384 dma_xfer((uint
*)0x20000, 0x20000, (uint
*)0);
386 dma_xfer((uint
*)0x40000, 0x40000, (uint
*)0);
388 dma_xfer((uint
*)0x80000, 0x80000, (uint
*)0);
390 dma_xfer((uint
*)0x100000, 0x100000, (uint
*)0);
392 dma_xfer((uint
*)0x200000, 0x200000, (uint
*)0);
394 dma_xfer((uint
*)0x400000, 0x400000, (uint
*)0);
396 for (i
= 1; i
< dram_size
/ 0x800000; i
++) {
397 dma_xfer((uint
*)(0x800000*i
), 0x800000, (uint
*)0);
401 * Enable errors for ECC.
403 ddr
->err_disable
= 0x00000000;
408 #endif /* CONFIG_DDR_ECC */