2 * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
8 * (C) Copyright 2003 Motorola Inc.
9 * Xianghua Xiao (X.Xiao@motorola.com)
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
35 #include <spd_sdram.h>
37 DECLARE_GLOBAL_DATA_PTR
;
39 void board_add_ram_info(int use_default
)
41 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
42 volatile ddr83xx_t
*ddr
= &immap
->ddr
;
45 printf(" (DDR%d", ((ddr
->sdram_cfg
& SDRAM_CFG_SDRAM_TYPE_MASK
)
46 >> SDRAM_CFG_SDRAM_TYPE_SHIFT
) - 1);
48 if (ddr
->sdram_cfg
& SDRAM_CFG_32_BE
)
53 if (ddr
->sdram_cfg
& SDRAM_CFG_ECC_EN
)
58 printf(", %s MHz)", strmhz(buf
, gd
->mem_clk
));
60 #if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE)
62 print_size (CFG_LBC_SDRAM_SIZE
* 1024 * 1024, " (local bus)");
66 #ifdef CONFIG_SPD_EEPROM
68 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
69 extern void dma_init(void);
70 extern uint
dma_check(void);
71 extern int dma_xfer(void *dest
, uint count
, void *src
);
75 #define CFG_READ_SPD i2c_read
79 * Convert picoseconds into clock cycles (rounding up if needed).
82 picos_to_clk(int picos
)
84 unsigned int mem_bus_clk
;
87 mem_bus_clk
= gd
->mem_clk
>> 1;
88 clks
= picos
/ (1000000000 / (mem_bus_clk
/ 1000));
89 if (picos
% (1000000000 / (mem_bus_clk
/ 1000)) != 0)
95 unsigned int banksize(unsigned char row_dens
)
97 return ((row_dens
>> 2) | ((row_dens
& 3) << 6)) << 24;
100 int read_spd(uint addr
)
107 static void spd_debug(spd_eeprom_t
*spd
)
109 printf ("\nDIMM type: %-18.18s\n", spd
->mpart
);
110 printf ("SPD size: %d\n", spd
->info_size
);
111 printf ("EEPROM size: %d\n", 1 << spd
->chip_size
);
112 printf ("Memory type: %d\n", spd
->mem_type
);
113 printf ("Row addr: %d\n", spd
->nrow_addr
);
114 printf ("Column addr: %d\n", spd
->ncol_addr
);
115 printf ("# of rows: %d\n", spd
->nrows
);
116 printf ("Row density: %d\n", spd
->row_dens
);
117 printf ("# of banks: %d\n", spd
->nbanks
);
118 printf ("Data width: %d\n",
119 256 * spd
->dataw_msb
+ spd
->dataw_lsb
);
120 printf ("Chip width: %d\n", spd
->primw
);
121 printf ("Refresh rate: %02X\n", spd
->refresh
);
122 printf ("CAS latencies: %02X\n", spd
->cas_lat
);
123 printf ("Write latencies: %02X\n", spd
->write_lat
);
124 printf ("tRP: %d\n", spd
->trp
);
125 printf ("tRCD: %d\n", spd
->trcd
);
128 #endif /* SPD_DEBUG */
132 volatile immap_t
*immap
= (immap_t
*)CFG_IMMR
;
133 volatile ddr83xx_t
*ddr
= &immap
->ddr
;
134 volatile law83xx_t
*ecm
= &immap
->sysconf
.ddrlaw
[0];
136 unsigned int n_ranks
;
137 unsigned int odt_rd_cfg
, odt_wr_cfg
;
138 unsigned char twr_clk
, twtr_clk
;
139 unsigned int sdram_type
;
140 unsigned int memsize
;
141 unsigned int law_size
;
142 unsigned char caslat
, caslat_ctrl
;
143 unsigned int trfc
, trfc_clk
, trfc_low
, trfc_high
;
144 unsigned int trcd_clk
, trtp_clk
;
145 unsigned char cke_min_clk
;
146 unsigned char add_lat
, wr_lat
;
147 unsigned char wr_data_delay
;
148 unsigned char four_act
;
150 unsigned char burstlen
;
151 unsigned char odt_cfg
, mode_odt_enable
;
152 unsigned int max_bus_clk
;
153 unsigned int max_data_rate
, effective_data_rate
;
154 unsigned int ddrc_clk
;
155 unsigned int refresh_clk
;
156 unsigned int sdram_cfg
;
157 unsigned int ddrc_ecc_enable
;
158 unsigned int pvr
= get_pvr();
160 /* Read SPD parameters with I2C */
161 CFG_READ_SPD(SPD_EEPROM_ADDRESS
, 0, 1, (uchar
*) & spd
, sizeof (spd
));
165 /* Check the memory type */
166 if (spd
.mem_type
!= SPD_MEMTYPE_DDR
&& spd
.mem_type
!= SPD_MEMTYPE_DDR2
) {
167 debug("DDR: Module mem type is %02X\n", spd
.mem_type
);
171 /* Check the number of physical bank */
172 if (spd
.mem_type
== SPD_MEMTYPE_DDR
) {
175 n_ranks
= (spd
.nrows
& 0x7) + 1;
179 printf("DDR: The number of physical bank is %02X\n", n_ranks
);
183 /* Check if the number of row of the module is in the range of DDRC */
184 if (spd
.nrow_addr
< 12 || spd
.nrow_addr
> 15) {
185 printf("DDR: Row number is out of range of DDRC, row=%02X\n",
190 /* Check if the number of col of the module is in the range of DDRC */
191 if (spd
.ncol_addr
< 8 || spd
.ncol_addr
> 11) {
192 printf("DDR: Col number is out of range of DDRC, col=%02X\n",
197 #ifdef CFG_DDRCDR_VALUE
199 * Adjust DDR II IO voltage biasing. It just makes it work.
201 if(spd
.mem_type
== SPD_MEMTYPE_DDR2
) {
202 immap
->sysconf
.ddrcdr
= CFG_DDRCDR_VALUE
;
208 * ODT configuration recommendation from DDR Controller Chapter.
210 odt_rd_cfg
= 0; /* Never assert ODT */
211 odt_wr_cfg
= 0; /* Never assert ODT */
212 if (spd
.mem_type
== SPD_MEMTYPE_DDR2
) {
213 odt_wr_cfg
= 1; /* Assert ODT on writes to CSn */
216 /* Setup DDR chip select register */
217 #ifdef CFG_83XX_DDR_USES_CS0
218 ddr
->csbnds
[0].csbnds
= (banksize(spd
.row_dens
) >> 24) - 1;
219 ddr
->cs_config
[0] = ( 1 << 31
222 | (spd
.nrow_addr
- 12) << 8
223 | (spd
.ncol_addr
- 8) );
225 debug("cs0_bnds = 0x%08x\n",ddr
->csbnds
[0].csbnds
);
226 debug("cs0_config = 0x%08x\n",ddr
->cs_config
[0]);
229 ddr
->csbnds
[1].csbnds
= ( (banksize(spd
.row_dens
) >> 8)
230 | ((banksize(spd
.row_dens
) >> 23) - 1) );
231 ddr
->cs_config
[1] = ( 1<<31
234 | (spd
.nrow_addr
-12) << 8
235 | (spd
.ncol_addr
-8) );
236 debug("cs1_bnds = 0x%08x\n",ddr
->csbnds
[1].csbnds
);
237 debug("cs1_config = 0x%08x\n",ddr
->cs_config
[1]);
241 ddr
->csbnds
[2].csbnds
= (banksize(spd
.row_dens
) >> 24) - 1;
242 ddr
->cs_config
[2] = ( 1 << 31
245 | (spd
.nrow_addr
- 12) << 8
246 | (spd
.ncol_addr
- 8) );
248 debug("cs2_bnds = 0x%08x\n",ddr
->csbnds
[2].csbnds
);
249 debug("cs2_config = 0x%08x\n",ddr
->cs_config
[2]);
252 ddr
->csbnds
[3].csbnds
= ( (banksize(spd
.row_dens
) >> 8)
253 | ((banksize(spd
.row_dens
) >> 23) - 1) );
254 ddr
->cs_config
[3] = ( 1<<31
257 | (spd
.nrow_addr
-12) << 8
258 | (spd
.ncol_addr
-8) );
259 debug("cs3_bnds = 0x%08x\n",ddr
->csbnds
[3].csbnds
);
260 debug("cs3_config = 0x%08x\n",ddr
->cs_config
[3]);
265 * Figure out memory size in Megabytes.
267 memsize
= n_ranks
* banksize(spd
.row_dens
) / 0x100000;
270 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
272 law_size
= 19 + __ilog2(memsize
);
275 * Set up LAWBAR for all of DDR.
277 ecm
->bar
= ((CFG_DDR_SDRAM_BASE
>>12) & 0xfffff);
278 ecm
->ar
= (LAWAR_EN
| LAWAR_TRGT_IF_DDR
| (LAWAR_SIZE
& law_size
));
279 debug("DDR:bar=0x%08x\n", ecm
->bar
);
280 debug("DDR:ar=0x%08x\n", ecm
->ar
);
283 * Find the largest CAS by locating the highest 1 bit
284 * in the spd.cas_lat field. Translate it to a DDR
285 * controller field value:
287 * CAS Lat DDR I DDR II Ctrl
288 * Clocks SPD Bit SPD Bit Value
289 * ------- ------- ------- -----
300 caslat
= __ilog2(spd
.cas_lat
);
301 if ((spd
.mem_type
== SPD_MEMTYPE_DDR
)
303 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd
.cas_lat
);
305 } else if (spd
.mem_type
== SPD_MEMTYPE_DDR2
306 && (caslat
< 2 || caslat
> 5)) {
307 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
311 debug("DDR: caslat SPD bit is %d\n", caslat
);
313 max_bus_clk
= 1000 *10 / (((spd
.clk_cycle
& 0xF0) >> 4) * 10
314 + (spd
.clk_cycle
& 0x0f));
315 max_data_rate
= max_bus_clk
* 2;
317 debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate
);
319 ddrc_clk
= gd
->mem_clk
/ 1000000;
320 effective_data_rate
= 0;
322 if (max_data_rate
>= 390 && max_data_rate
< 460) { /* it is DDR 400 */
323 if (ddrc_clk
<= 460 && ddrc_clk
> 350) {
324 /* DDR controller clk at 350~460 */
325 effective_data_rate
= 400; /* 5ns */
327 } else if (ddrc_clk
<= 350 && ddrc_clk
> 280) {
328 /* DDR controller clk at 280~350 */
329 effective_data_rate
= 333; /* 6ns */
330 if (spd
.clk_cycle2
== 0x60)
334 } else if (ddrc_clk
<= 280 && ddrc_clk
> 230) {
335 /* DDR controller clk at 230~280 */
336 effective_data_rate
= 266; /* 7.5ns */
337 if (spd
.clk_cycle3
== 0x75)
339 else if (spd
.clk_cycle2
== 0x75)
343 } else if (ddrc_clk
<= 230 && ddrc_clk
> 90) {
344 /* DDR controller clk at 90~230 */
345 effective_data_rate
= 200; /* 10ns */
346 if (spd
.clk_cycle3
== 0xa0)
348 else if (spd
.clk_cycle2
== 0xa0)
353 } else if (max_data_rate
>= 323) { /* it is DDR 333 */
354 if (ddrc_clk
<= 350 && ddrc_clk
> 280) {
355 /* DDR controller clk at 280~350 */
356 effective_data_rate
= 333; /* 6ns */
358 } else if (ddrc_clk
<= 280 && ddrc_clk
> 230) {
359 /* DDR controller clk at 230~280 */
360 effective_data_rate
= 266; /* 7.5ns */
361 if (spd
.clk_cycle2
== 0x75)
365 } else if (ddrc_clk
<= 230 && ddrc_clk
> 90) {
366 /* DDR controller clk at 90~230 */
367 effective_data_rate
= 200; /* 10ns */
368 if (spd
.clk_cycle3
== 0xa0)
370 else if (spd
.clk_cycle2
== 0xa0)
375 } else if (max_data_rate
>= 256) { /* it is DDR 266 */
376 if (ddrc_clk
<= 350 && ddrc_clk
> 280) {
377 /* DDR controller clk at 280~350 */
378 printf("DDR: DDR controller freq is more than "
379 "max data rate of the module\n");
381 } else if (ddrc_clk
<= 280 && ddrc_clk
> 230) {
382 /* DDR controller clk at 230~280 */
383 effective_data_rate
= 266; /* 7.5ns */
385 } else if (ddrc_clk
<= 230 && ddrc_clk
> 90) {
386 /* DDR controller clk at 90~230 */
387 effective_data_rate
= 200; /* 10ns */
388 if (spd
.clk_cycle2
== 0xa0)
391 } else if (max_data_rate
>= 190) { /* it is DDR 200 */
392 if (ddrc_clk
<= 350 && ddrc_clk
> 230) {
393 /* DDR controller clk at 230~350 */
394 printf("DDR: DDR controller freq is more than "
395 "max data rate of the module\n");
397 } else if (ddrc_clk
<= 230 && ddrc_clk
> 90) {
398 /* DDR controller clk at 90~230 */
399 effective_data_rate
= 200; /* 10ns */
404 debug("DDR:Effective data rate is: %dMhz\n", effective_data_rate
);
405 debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat
);
408 * Errata DDR6 work around: input enable 2 cycles earlier.
409 * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
411 if(PVR_MAJ(pvr
) <= 1 && spd
.mem_type
== SPD_MEMTYPE_DDR
){
413 ddr
->debug_reg
= 0x201c0000; /* CL=2 */
414 else if (caslat
== 3)
415 ddr
->debug_reg
= 0x202c0000; /* CL=2.5 */
416 else if (caslat
== 4)
417 ddr
->debug_reg
= 0x202c0000; /* CL=3.0 */
419 __asm__
__volatile__ ("sync");
421 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr
->debug_reg
);
425 * Convert caslat clocks to DDR controller value.
426 * Force caslat_ctrl to be DDR Controller field-sized.
428 if (spd
.mem_type
== SPD_MEMTYPE_DDR
) {
429 caslat_ctrl
= (caslat
+ 1) & 0x07;
431 caslat_ctrl
= (2 * caslat
- 1) & 0x0f;
434 debug("DDR: effective data rate is %d MHz\n", effective_data_rate
);
435 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
436 caslat
, caslat_ctrl
);
440 * Avoid writing for DDR I.
442 if (spd
.mem_type
== SPD_MEMTYPE_DDR2
) {
443 unsigned char taxpd_clk
= 8; /* By the book. */
444 unsigned char tmrd_clk
= 2; /* By the book. */
445 unsigned char act_pd_exit
= 2; /* Empirical? */
446 unsigned char pre_pd_exit
= 6; /* Empirical? */
448 ddr
->timing_cfg_0
= (0
449 | ((act_pd_exit
& 0x7) << 20) /* ACT_PD_EXIT */
450 | ((pre_pd_exit
& 0x7) << 16) /* PRE_PD_EXIT */
451 | ((taxpd_clk
& 0xf) << 8) /* ODT_PD_EXIT */
452 | ((tmrd_clk
& 0xf) << 0) /* MRS_CYC */
454 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr
->timing_cfg_0
);
458 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
459 * use conservative value.
460 * For DDR II, they are bytes 36 and 37, in quarter nanos.
463 if (spd
.mem_type
== SPD_MEMTYPE_DDR
) {
464 twr_clk
= 3; /* Clocks */
465 twtr_clk
= 1; /* Clocks */
467 twr_clk
= picos_to_clk(spd
.twr
* 250);
468 twtr_clk
= picos_to_clk(spd
.twtr
* 250);
472 * Calculate Trfc, in picos.
473 * DDR I: Byte 42 straight up in ns.
474 * DDR II: Byte 40 and 42 swizzled some, in ns.
476 if (spd
.mem_type
== SPD_MEMTYPE_DDR
) {
477 trfc
= spd
.trfc
* 1000; /* up to ps */
479 unsigned int byte40_table_ps
[8] = {
490 trfc
= (((spd
.trctrfc_ext
& 0x1) * 256) + spd
.trfc
) * 1000
491 + byte40_table_ps
[(spd
.trctrfc_ext
>> 1) & 0x7];
493 trfc_clk
= picos_to_clk(trfc
);
496 * Trcd, Byte 29, from quarter nanos to ps and clocks.
498 trcd_clk
= picos_to_clk(spd
.trcd
* 250) & 0x7;
501 * Convert trfc_clk to DDR controller fields. DDR I should
502 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
503 * 83xx controller has an extended REFREC field of three bits.
504 * The controller automatically adds 8 clocks to this value,
505 * so preadjust it down 8 first before splitting it up.
507 trfc_low
= (trfc_clk
- 8) & 0xf;
508 trfc_high
= ((trfc_clk
- 8) >> 4) & 0x3;
511 (((picos_to_clk(spd
.trp
* 250) & 0x07) << 28 ) | /* PRETOACT */
512 ((picos_to_clk(spd
.tras
* 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
513 (trcd_clk
<< 20 ) | /* ACTTORW */
514 (caslat_ctrl
<< 16 ) | /* CASLAT */
515 (trfc_low
<< 12 ) | /* REFEC */
516 ((twr_clk
& 0x07) << 8) | /* WRRREC */
517 ((picos_to_clk(spd
.trrd
* 250) & 0x07) << 4) | /* ACTTOACT */
518 ((twtr_clk
& 0x07) << 0) /* WRTORD */
524 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
525 * which comes from Trcd, and also note that:
526 * add_lat + caslat must be >= 4
529 if (spd
.mem_type
== SPD_MEMTYPE_DDR2
530 && (odt_wr_cfg
|| odt_rd_cfg
)
532 add_lat
= trcd_clk
- 1;
533 if ((add_lat
+ caslat
) < 4) {
540 * Historically 0x2 == 4/8 clock delay.
541 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
548 * Minimum CKE Pulse Width.
549 * Four Activate Window
551 if (spd
.mem_type
== SPD_MEMTYPE_DDR
) {
553 * This is a lie. It should really be 1, but if it is
554 * set to 1, bits overlap into the old controller's
555 * otherwise unused ACSM field. If we leave it 0, then
556 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
560 trtp_clk
= 2; /* By the book. */
561 cke_min_clk
= 1; /* By the book. */
562 four_act
= 1; /* By the book. */
567 /* Convert SPD value from quarter nanos to picos. */
568 trtp_clk
= picos_to_clk(spd
.trtp
* 250);
570 cke_min_clk
= 3; /* By the book. */
571 four_act
= picos_to_clk(37500); /* By the book. 1k pages? */
575 * Empirically set ~MCAS-to-preamble override for DDR 2.
576 * Your milage will vary.
579 if (spd
.mem_type
== SPD_MEMTYPE_DDR2
) {
580 if (effective_data_rate
== 266) {
581 cpo
= 0x4; /* READ_LAT + 1/2 */
582 } else if (effective_data_rate
== 333 || effective_data_rate
== 400) {
583 cpo
= 0x7; /* READ_LAT + 5/4 */
585 /* Automatic calibration */
590 ddr
->timing_cfg_2
= (0
591 | ((add_lat
& 0x7) << 28) /* ADD_LAT */
592 | ((cpo
& 0x1f) << 23) /* CPO */
593 | ((wr_lat
& 0x7) << 19) /* WR_LAT */
594 | ((trtp_clk
& 0x7) << 13) /* RD_TO_PRE */
595 | ((wr_data_delay
& 0x7) << 10) /* WR_DATA_DELAY */
596 | ((cke_min_clk
& 0x7) << 6) /* CKE_PLS */
597 | ((four_act
& 0x1f) << 0) /* FOUR_ACT */
600 debug("DDR:timing_cfg_1=0x%08x\n", ddr
->timing_cfg_1
);
601 debug("DDR:timing_cfg_2=0x%08x\n", ddr
->timing_cfg_2
);
603 /* Check DIMM data bus width */
604 if (spd
.dataw_lsb
== 0x20) {
605 if (spd
.mem_type
== SPD_MEMTYPE_DDR
)
606 burstlen
= 0x03; /* 32 bit data bus, burst len is 8 */
608 burstlen
= 0x02; /* 32 bit data bus, burst len is 4 */
609 debug("\n DDR DIMM: data bus width is 32 bit");
611 burstlen
= 0x02; /* Others act as 64 bit bus, burst len is 4 */
612 debug("\n DDR DIMM: data bus width is 64 bit");
615 /* Is this an ECC DDR chip? */
616 if (spd
.config
== 0x02)
617 debug(" with ECC\n");
619 debug(" without ECC\n");
621 /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
622 Burst type is sequential
624 if (spd
.mem_type
== SPD_MEMTYPE_DDR
) {
627 ddr
->sdram_mode
= 0x50 | burstlen
; /* CL=1.5 */
630 ddr
->sdram_mode
= 0x20 | burstlen
; /* CL=2.0 */
633 ddr
->sdram_mode
= 0x60 | burstlen
; /* CL=2.5 */
636 ddr
->sdram_mode
= 0x30 | burstlen
; /* CL=3.0 */
639 printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
643 mode_odt_enable
= 0x0; /* Default disabled */
644 if (odt_wr_cfg
|| odt_rd_cfg
) {
646 * Bits 6 and 2 in Extended MRS(1)
647 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
648 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
650 mode_odt_enable
= 0x40; /* 150 Ohm */
655 | (1 << (16 + 10)) /* DQS Differential disable */
656 | (add_lat
<< (16 + 3)) /* Additive Latency in EMRS1 */
657 | (mode_odt_enable
<< 16) /* ODT Enable in EMRS1 */
658 | ((twr_clk
- 1) << 9) /* Write Recovery Autopre */
659 | (caslat
<< 4) /* caslat */
660 | (burstlen
<< 0) /* Burst length */
663 debug("DDR:sdram_mode=0x%08x\n", ddr
->sdram_mode
);
666 * Clear EMRS2 and EMRS3.
668 ddr
->sdram_mode2
= 0;
669 debug("DDR: sdram_mode2 = 0x%08x\n", ddr
->sdram_mode2
);
671 switch (spd
.refresh
) {
674 refresh_clk
= picos_to_clk(15625000);
678 refresh_clk
= picos_to_clk(3900000);
682 refresh_clk
= picos_to_clk(7800000);
686 refresh_clk
= picos_to_clk(31300000);
690 refresh_clk
= picos_to_clk(62500000);
694 refresh_clk
= picos_to_clk(125000000);
702 * Set BSTOPRE to 0x100 for page mode
703 * If auto-charge is used, set BSTOPRE = 0
705 ddr
->sdram_interval
= ((refresh_clk
& 0x3fff) << 16) | 0x100;
706 debug("DDR:sdram_interval=0x%08x\n", ddr
->sdram_interval
);
712 #ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
713 if (odt_rd_cfg
| odt_wr_cfg
) {
714 odt_cfg
= 0x2; /* ODT to IOs during reads */
717 if (spd
.mem_type
== SPD_MEMTYPE_DDR2
) {
719 | (0 << 26) /* True DQS */
720 | (odt_cfg
<< 21) /* ODT only read */
721 | (1 << 12) /* 1 refresh at a time */
724 debug("DDR: sdram_cfg2 = 0x%08x\n", ddr
->sdram_cfg2
);
727 #ifdef CFG_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
728 ddr
->sdram_clk_cntl
= CFG_DDR_SDRAM_CLK_CNTL
;
730 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr
->sdram_clk_cntl
);
737 * Figure out the settings for the sdram_cfg register. Build up
738 * the value in 'sdram_cfg' before writing since the write into
739 * the register will actually enable the memory controller, and all
740 * settings must be done before enabling.
742 * sdram_cfg[0] = 1 (ddr sdram logic enable)
743 * sdram_cfg[1] = 1 (self-refresh-enable)
744 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
747 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
748 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
750 if (spd
.mem_type
== SPD_MEMTYPE_DDR
)
751 sdram_type
= SDRAM_CFG_SDRAM_TYPE_DDR1
;
753 sdram_type
= SDRAM_CFG_SDRAM_TYPE_DDR2
;
756 | SDRAM_CFG_MEM_EN
/* DDR enable */
757 | SDRAM_CFG_SREN
/* Self refresh */
758 | sdram_type
/* SDRAM type */
761 /* sdram_cfg[3] = RD_EN - registered DIMM enable */
762 if (spd
.mod_attr
& 0x02)
763 sdram_cfg
|= SDRAM_CFG_RD_EN
;
765 /* The DIMM is 32bit width */
766 if (spd
.dataw_lsb
== 0x20) {
767 if (spd
.mem_type
== SPD_MEMTYPE_DDR
)
768 sdram_cfg
|= SDRAM_CFG_32_BE
| SDRAM_CFG_8_BE
;
769 if (spd
.mem_type
== SPD_MEMTYPE_DDR2
)
770 sdram_cfg
|= SDRAM_CFG_32_BE
;
775 #if defined(CONFIG_DDR_ECC)
776 /* Enable ECC with sdram_cfg[2] */
777 if (spd
.config
== 0x02) {
778 sdram_cfg
|= 0x20000000;
780 /* disable error detection */
781 ddr
->err_disable
= ~ECC_ERROR_ENABLE
;
782 /* set single bit error threshold to maximum value,
783 * reset counter to zero */
784 ddr
->err_sbe
= (255 << ECC_ERROR_MAN_SBET_SHIFT
) |
785 (0 << ECC_ERROR_MAN_SBEC_SHIFT
);
788 debug("DDR:err_disable=0x%08x\n", ddr
->err_disable
);
789 debug("DDR:err_sbe=0x%08x\n", ddr
->err_sbe
);
791 debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable
? "ON":"OFF");
793 #if defined(CONFIG_DDR_2T_TIMING)
795 * Enable 2T timing by setting sdram_cfg[16].
797 sdram_cfg
|= SDRAM_CFG_2T_EN
;
799 /* Enable controller, and GO! */
800 ddr
->sdram_cfg
= sdram_cfg
;
804 debug("DDR:sdram_cfg=0x%08x\n", ddr
->sdram_cfg
);
805 return memsize
; /*in MBytes*/
807 #endif /* CONFIG_SPD_EEPROM */
809 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
811 * Use timebase counter, get_timer() is not availabe
812 * at this point of initialization yet.
814 static __inline__
unsigned long get_tbms (void)
817 unsigned long tbu1
, tbu2
;
819 unsigned long long tmp
;
821 ulong tbclk
= get_tbclk();
823 /* get the timebase ticks */
825 asm volatile ("mftbu %0":"=r" (tbu1
):);
826 asm volatile ("mftb %0":"=r" (tbl
):);
827 asm volatile ("mftbu %0":"=r" (tbu2
):);
828 } while (tbu1
!= tbu2
);
830 /* convert ticks to ms */
831 tmp
= (unsigned long long)(tbu1
);
833 tmp
+= (unsigned long long)(tbl
);
834 ms
= tmp
/(tbclk
/1000);
840 * Initialize all of memory for ECC, then enable errors.
842 /* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
843 void ddr_enable_ecc(unsigned int dram_size
)
845 volatile immap_t
*immap
= (immap_t
*)CFG_IMMR
;
846 volatile ddr83xx_t
*ddr
= &immap
->ddr
;
847 unsigned long t_start
, t_end
;
850 unsigned int pattern
[2];
851 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
855 t_start
= get_tbms();
856 pattern
[0] = 0xdeadbeef;
857 pattern
[1] = 0xdeadbeef;
859 #if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
860 debug("ddr init: CPU FP write method\n");
862 for (p
= 0; p
< (u64
*)(size
); p
++) {
863 ppcDWstore((u32
*)p
, pattern
);
865 __asm__
__volatile__ ("sync");
867 debug("ddr init: DMA method\n");
869 for (p
= 0; p
< (u64
*)(size
); p
++) {
870 ppcDWstore((u32
*)p
, pattern
);
872 __asm__
__volatile__ ("sync");
874 /* Initialise DMA for direct transfer */
876 /* Start DMA to transfer */
877 dma_xfer((uint
*)0x2000, 0x2000, (uint
*)0); /* 8K */
878 dma_xfer((uint
*)0x4000, 0x4000, (uint
*)0); /* 16K */
879 dma_xfer((uint
*)0x8000, 0x8000, (uint
*)0); /* 32K */
880 dma_xfer((uint
*)0x10000, 0x10000, (uint
*)0); /* 64K */
881 dma_xfer((uint
*)0x20000, 0x20000, (uint
*)0); /* 128K */
882 dma_xfer((uint
*)0x40000, 0x40000, (uint
*)0); /* 256K */
883 dma_xfer((uint
*)0x80000, 0x80000, (uint
*)0); /* 512K */
884 dma_xfer((uint
*)0x100000, 0x100000, (uint
*)0); /* 1M */
885 dma_xfer((uint
*)0x200000, 0x200000, (uint
*)0); /* 2M */
886 dma_xfer((uint
*)0x400000, 0x400000, (uint
*)0); /* 4M */
888 for (i
= 1; i
< dram_size
/ 0x800000; i
++) {
889 dma_xfer((uint
*)(0x800000*i
), 0x800000, (uint
*)0);
896 debug("\nREADY!!\n");
897 debug("ddr init duration: %ld ms\n", t_end
- t_start
);
899 /* Clear All ECC Errors */
900 if ((ddr
->err_detect
& ECC_ERROR_DETECT_MME
) == ECC_ERROR_DETECT_MME
)
901 ddr
->err_detect
|= ECC_ERROR_DETECT_MME
;
902 if ((ddr
->err_detect
& ECC_ERROR_DETECT_MBE
) == ECC_ERROR_DETECT_MBE
)
903 ddr
->err_detect
|= ECC_ERROR_DETECT_MBE
;
904 if ((ddr
->err_detect
& ECC_ERROR_DETECT_SBE
) == ECC_ERROR_DETECT_SBE
)
905 ddr
->err_detect
|= ECC_ERROR_DETECT_SBE
;
906 if ((ddr
->err_detect
& ECC_ERROR_DETECT_MSE
) == ECC_ERROR_DETECT_MSE
)
907 ddr
->err_detect
|= ECC_ERROR_DETECT_MSE
;
909 /* Disable ECC-Interrupts */
910 ddr
->err_int_en
&= ECC_ERR_INT_DISABLE
;
912 /* Enable errors for ECC */
913 ddr
->err_disable
&= ECC_ERROR_ENABLE
;
915 __asm__
__volatile__ ("sync");
916 __asm__
__volatile__ ("isync");
918 #endif /* CONFIG_DDR_ECC */