2 * Copyright 2004,2007-2009 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <fsl_esdhc.h>
33 #include <asm/cache.h>
36 DECLARE_GLOBAL_DATA_PTR
;
46 char buf1
[32], buf2
[32];
47 #ifdef CONFIG_DDR_CLK_FREQ
48 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
49 u32 ddr_ratio
= ((gur
->porpllsr
) & MPC85xx_PORPLLSR_DDR_RATIO
)
50 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT
;
59 major
&= 0x7; /* the msb of this nibble is a mfg code */
63 if (cpu_numcores() > 1) {
65 puts("Unicore software on multiprocessor system!!\n"
66 "To enable mutlticore build define CONFIG_MP\n");
68 volatile ccsr_pic_t
*pic
= (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR
);
69 printf("CPU%d: ", pic
->whoami
);
77 if (IS_E_PROCESSOR(svr
))
80 printf(", Version: %d.%d, (0x%08x)\n", major
, minor
, svr
);
90 case PVR_FAM(PVR_85xx
):
98 if (PVR_MEM(pvr
) == 0x03)
101 printf(", Version: %d.%d, (0x%08x)\n", major
, minor
, pvr
);
103 get_sys_info(&sysinfo
);
105 puts("Clock Configuration:");
106 for (i
= 0; i
< cpu_numcores(); i
++) {
109 printf("CPU%d:%-4s MHz, ",
110 i
,strmhz(buf1
, sysinfo
.freqProcessor
[i
]));
112 printf("\n CCB:%-4s MHz,\n", strmhz(buf1
, sysinfo
.freqSystemBus
));
116 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
117 strmhz(buf1
, sysinfo
.freqDDRBus
/2),
118 strmhz(buf2
, sysinfo
.freqDDRBus
));
121 printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ",
122 strmhz(buf1
, sysinfo
.freqDDRBus
/2),
123 strmhz(buf2
, sysinfo
.freqDDRBus
));
126 printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ",
127 strmhz(buf1
, sysinfo
.freqDDRBus
/2),
128 strmhz(buf2
, sysinfo
.freqDDRBus
));
132 if (sysinfo
.freqLocalBus
> LCRR_CLKDIV
)
133 printf("LBC:%-4s MHz\n", strmhz(buf1
, sysinfo
.freqLocalBus
));
135 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
136 sysinfo
.freqLocalBus
);
139 printf("CPM: %s MHz\n", strmhz(buf1
, sysinfo
.freqSystemBus
));
143 printf(" QE:%-4s MHz\n", strmhz(buf1
, sysinfo
.freqQE
));
146 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
152 /* ------------------------------------------------------------------------- */
154 int do_reset (cmd_tbl_t
*cmdtp
, bd_t
*bd
, int flag
, int argc
, char *argv
[])
156 /* Everything after the first generation of PQ3 parts has RSTCR */
157 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
158 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
159 unsigned long val
, msr
;
162 * Initiate hard reset in debug control register DBCR0
163 * Make sure MSR[DE] = 1. This only resets the core.
173 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
174 out_be32(&gur
->rstcr
, 0x2); /* HRESET_REQ */
183 * Get timebase clock frequency
185 unsigned long get_tbclk (void)
187 #ifdef CONFIG_FSL_CORENET
188 return (gd
->bus_clk
+ 8) / 16;
190 return (gd
->bus_clk
+ 4UL)/8UL;
195 #if defined(CONFIG_WATCHDOG)
199 int re_enable
= disable_interrupts();
200 reset_85xx_watchdog();
201 if (re_enable
) enable_interrupts();
205 reset_85xx_watchdog(void)
208 * Clear TSR(WIS) bit by writing 1
211 val
= mfspr(SPRN_TSR
);
213 mtspr(SPRN_TSR
, val
);
215 #endif /* CONFIG_WATCHDOG */
218 * Configures a UPM. The function requires the respective MxMR to be set
219 * before calling this function. "size" is the number or entries, not a sizeof.
221 void upmconfig (uint upm
, uint
* table
, uint size
)
223 int i
, mdr
, mad
, old_mad
= 0;
225 volatile ccsr_lbc_t
*lbc
= (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR
);
226 volatile u32
*brp
,*orp
;
227 volatile u8
* dummy
= NULL
;
233 upmmask
= BR_MS_UPMA
;
237 upmmask
= BR_MS_UPMB
;
241 upmmask
= BR_MS_UPMC
;
244 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__
, upm
);
248 /* Find the address for the dummy write transaction */
249 for (brp
= &lbc
->br0
, orp
= &lbc
->or0
, i
= 0; i
< 8;
250 i
++, brp
+= 2, orp
+= 2) {
252 /* Look for a valid BR with selected UPM */
253 if ((in_be32(brp
) & (BR_V
| BR_MSEL
)) == (BR_V
| upmmask
)) {
254 dummy
= (volatile u8
*)(in_be32(brp
) & BR_BA
);
260 printf("Error: %s() could not find matching BR\n", __FUNCTION__
);
264 for (i
= 0; i
< size
; i
++) {
266 out_be32(mxmr
, (in_be32(mxmr
) & 0x4fffffc0) | MxMR_OP_WARR
| i
);
268 out_be32(&lbc
->mdr
, table
[i
]);
270 mdr
= in_be32(&lbc
->mdr
);
272 *(volatile u8
*)dummy
= 0;
275 mad
= in_be32(mxmr
) & MxMR_MAD_MSK
;
276 } while (mad
<= old_mad
&& !(!mad
&& i
== (size
-1)));
279 out_be32(mxmr
, (in_be32(mxmr
) & 0x4fffffc0) | MxMR_OP_NORM
);
283 * Initializes on-chip MMC controllers.
284 * to override, implement board_mmc_init()
286 int cpu_mmc_init(bd_t
*bis
)
288 #ifdef CONFIG_FSL_ESDHC
289 return fsl_esdhc_mmc_init(bis
);