cpu/mpc85xx/cpu.c

   1 /*
   2  * Copyright 2004,2007 Freescale Semiconductor, Inc.
   3  * (C) Copyright 2002, 2003 Motorola Inc.
   4  * Xianghua Xiao (X.Xiao@motorola.com)
   5  *
   6  * (C) Copyright 2000
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <watchdog.h>
  30 #include <command.h>
  31 #include <asm/cache.h>
  32
  33 int checkcpu (void)
  34 {
  35         sys_info_t sysinfo;
  36         uint lcrr;              /* local bus clock ratio register */
  37         uint clkdiv;            /* clock divider portion of lcrr */
  38         uint pvr, svr;
  39         uint fam;
  40         uint ver;
  41         uint major, minor;
  42
  43         svr = get_svr();
  44         ver = SVR_VER(svr);
  45         major = SVR_MAJ(svr);
  46         minor = SVR_MIN(svr);
  47
  48         puts("CPU:   ");
  49         switch (ver) {
  50         case SVR_8540:
  51                 puts("8540");
  52                 break;
  53         case SVR_8541:
  54                 puts("8541");
  55                 break;
  56         case SVR_8555:
  57                 puts("8555");
  58                 break;
  59         case SVR_8560:
  60                 puts("8560");
  61                 break;
  62         case SVR_8548:
  63                 puts("8548");
  64                 break;
  65         case SVR_8548_E:
  66                 puts("8548_E");
  67                 break;
  68         case SVR_8544:
  69                 puts("8544");
  70                 break;
  71         case SVR_8544_E:
  72                 puts("8544_E");
  73                 break;
  74         case SVR_8568_E:
  75                 puts("8568_E");
  76                 break;
  77         default:
  78                 puts("Unknown");
  79                 break;
  80         }
  81         printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  82
  83         pvr = get_pvr();
  84         fam = PVR_FAM(pvr);
  85         ver = PVR_VER(pvr);
  86         major = PVR_MAJ(pvr);
  87         minor = PVR_MIN(pvr);
  88
  89         printf("Core:  ");
  90         switch (fam) {
  91         case PVR_FAM(PVR_85xx):
  92             puts("E500");
  93             break;
  94         default:
  95             puts("Unknown");
  96             break;
  97         }
  98         printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
  99
 100         get_sys_info(&sysinfo);
 101
 102         puts("Clock Configuration:\n");
 103         printf("       CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
 104         printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
 105         printf("       DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
 106
 107 #if defined(CFG_LBC_LCRR)
 108         lcrr = CFG_LBC_LCRR;
 109 #else
 110         {
 111             volatile immap_t *immap = (immap_t *)CFG_IMMR;
 112             volatile ccsr_lbc_t *lbc= &immap->im_lbc;
 113
 114             lcrr = lbc->lcrr;
 115         }
 116 #endif
 117         clkdiv = lcrr & 0x0f;
 118         if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
 119 #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
 120                 /*
 121                  * Yes, the entire PQ38 family use the same
 122                  * bit-representation for twice the clock divider values.
 123                  */
 124                  clkdiv *= 2;
 125 #endif
 126                 printf("LBC:%4lu MHz\n",
 127                        sysinfo.freqSystemBus / 1000000 / clkdiv);
 128         } else {
 129                 printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
 130         }
 131
 132         if (ver == SVR_8560) {
 133                 printf("CPM:  %lu Mhz\n",
 134                        sysinfo.freqSystemBus / 1000000);
 135         }
 136
 137         puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");
 138
 139         return 0;
 140 }
 141
 142
 143 /* ------------------------------------------------------------------------- */
 144
 145 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 146 {
 147         uint pvr;
 148         uint ver;
 149         pvr = get_pvr();
 150         ver = PVR_VER(pvr);
 151         if (ver & 1){
 152         /* e500 v2 core has reset control register */
 153                 volatile unsigned int * rstcr;
 154                 rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
 155                 *rstcr = 0x2;           /* HRESET_REQ */
 156         }else{
 157         /*
 158          * Initiate hard reset in debug control register DBCR0
 159          * Make sure MSR[DE] = 1
 160          */
 161                 unsigned long val, msr;
 162
 163                 msr = mfmsr ();
 164                 msr |= MSR_DE;
 165                 mtmsr (msr);
 166
 167                 val = mfspr(DBCR0);
 168                 val |= 0x70000000;
 169                 mtspr(DBCR0,val);
 170         }
 171         return 1;
 172 }
 173
 174
 175 /*
 176  * Get timebase clock frequency
 177  */
 178 unsigned long get_tbclk (void)
 179 {
 180
 181         sys_info_t  sys_info;
 182
 183         get_sys_info(&sys_info);
 184         return ((sys_info.freqSystemBus + 7L) / 8L);
 185 }
 186
 187
 188 #if defined(CONFIG_WATCHDOG)
 189 void
 190 watchdog_reset(void)
 191 {
 192         int re_enable = disable_interrupts();
 193         reset_85xx_watchdog();
 194         if (re_enable) enable_interrupts();
 195 }
 196
 197 void
 198 reset_85xx_watchdog(void)
 199 {
 200         /*
 201          * Clear TSR(WIS) bit by writing 1
 202          */
 203         unsigned long val;
 204         val = mfspr(SPRN_TSR);
 205         val |= TSR_WIS;
 206         mtspr(SPRN_TSR, val);
 207 }
 208 #endif  /* CONFIG_WATCHDOG */
 209
 210 #if defined(CONFIG_DDR_ECC)
 211 void dma_init(void) {
 212         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 213         volatile ccsr_dma_t *dma = &immap->im_dma;
 214
 215         dma->satr0 = 0x02c40000;
 216         dma->datr0 = 0x02c40000;
 217         dma->sr0 = 0xfffffff; /* clear any errors */
 218         asm("sync; isync; msync");
 219         return;
 220 }
 221
 222 uint dma_check(void) {
 223         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 224         volatile ccsr_dma_t *dma = &immap->im_dma;
 225         volatile uint status = dma->sr0;
 226
 227         /* While the channel is busy, spin */
 228         while((status & 4) == 4) {
 229                 status = dma->sr0;
 230         }
 231
 232         /* clear MR0[CS] channel start bit */
 233         dma->mr0 &= 0x00000001;
 234         asm("sync;isync;msync");
 235
 236         if (status != 0) {
 237                 printf ("DMA Error: status = %x\n", status);
 238         }
 239         return status;
 240 }
 241
 242 int dma_xfer(void *dest, uint count, void *src) {
 243         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 244         volatile ccsr_dma_t *dma = &immap->im_dma;
 245
 246         dma->dar0 = (uint) dest;
 247         dma->sar0 = (uint) src;
 248         dma->bcr0 = count;
 249         dma->mr0 = 0xf000004;
 250         asm("sync;isync;msync");
 251         dma->mr0 = 0xf000005;
 252         asm("sync;isync;msync");
 253         return dma_check();
 254 }
 255 #endif