cpu/mpc85xx/cpu.c

   1 /*
   2  * Copyright 2004,2007 Freescale Semiconductor, Inc.
   3  * (C) Copyright 2002, 2003 Motorola Inc.
   4  * Xianghua Xiao (X.Xiao@motorola.com)
   5  *
   6  * (C) Copyright 2000
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <watchdog.h>
  30 #include <command.h>
  31 #include <asm/cache.h>
  32
  33 int checkcpu (void)
  34 {
  35         sys_info_t sysinfo;
  36         uint lcrr;              /* local bus clock ratio register */
  37         uint clkdiv;            /* clock divider portion of lcrr */
  38         uint pvr, svr;
  39         uint fam;
  40         uint ver;
  41         uint major, minor;
  42         u32 ddr_ratio;
  43         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  44
  45         svr = get_svr();
  46         ver = SVR_VER(svr);
  47         major = SVR_MAJ(svr);
  48         minor = SVR_MIN(svr);
  49
  50         puts("CPU:   ");
  51         switch (ver) {
  52         case SVR_8540:
  53                 puts("8540");
  54                 break;
  55         case SVR_8541:
  56                 puts("8541");
  57                 break;
  58         case SVR_8555:
  59                 puts("8555");
  60                 break;
  61         case SVR_8560:
  62                 puts("8560");
  63                 break;
  64         case SVR_8548:
  65                 puts("8548");
  66                 break;
  67         case SVR_8548_E:
  68                 puts("8548_E");
  69                 break;
  70         case SVR_8544:
  71                 puts("8544");
  72                 break;
  73         case SVR_8544_E:
  74                 puts("8544_E");
  75                 break;
  76         case SVR_8568_E:
  77                 puts("8568_E");
  78                 break;
  79         default:
  80                 puts("Unknown");
  81                 break;
  82         }
  83         printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  84
  85         pvr = get_pvr();
  86         fam = PVR_FAM(pvr);
  87         ver = PVR_VER(pvr);
  88         major = PVR_MAJ(pvr);
  89         minor = PVR_MIN(pvr);
  90
  91         printf("Core:  ");
  92         switch (fam) {
  93         case PVR_FAM(PVR_85xx):
  94             puts("E500");
  95             break;
  96         default:
  97             puts("Unknown");
  98             break;
  99         }
 100         printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
 101
 102         get_sys_info(&sysinfo);
 103
 104         puts("Clock Configuration:\n");
 105         printf("       CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
 106         printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
 107
 108         ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
 109         switch (ddr_ratio) {
 110         case 0x0:
 111                 printf("       DDR:%4lu MHz, ", sysinfo.freqDDRBus / 2000000);
 112                 break;
 113         case 0x7:
 114                 printf("       DDR:%4lu MHz (Synchronous), ", sysinfo.freqDDRBus / 2000000);
 115                 break;
 116         default:
 117                 printf("       DDR:%4lu MHz (Asynchronous), ", sysinfo.freqDDRBus / 2000000);
 118                 break;
 119         }
 120
 121 #if defined(CFG_LBC_LCRR)
 122         lcrr = CFG_LBC_LCRR;
 123 #else
 124         {
 125             volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 126
 127             lcrr = lbc->lcrr;
 128         }
 129 #endif
 130         clkdiv = lcrr & 0x0f;
 131         if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
 132 #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
 133                 /*
 134                  * Yes, the entire PQ38 family use the same
 135                  * bit-representation for twice the clock divider values.
 136                  */
 137                  clkdiv *= 2;
 138 #endif
 139                 printf("LBC:%4lu MHz\n",
 140                        sysinfo.freqSystemBus / 1000000 / clkdiv);
 141         } else {
 142                 printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
 143         }
 144
 145         if (ver == SVR_8560) {
 146                 printf("CPM:  %lu Mhz\n",
 147                        sysinfo.freqSystemBus / 1000000);
 148         }
 149
 150         puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");
 151
 152         return 0;
 153 }
 154
 155
 156 /* ------------------------------------------------------------------------- */
 157
 158 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 159 {
 160         uint pvr;
 161         uint ver;
 162         pvr = get_pvr();
 163         ver = PVR_VER(pvr);
 164         if (ver & 1){
 165         /* e500 v2 core has reset control register */
 166                 volatile unsigned int * rstcr;
 167                 rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
 168                 *rstcr = 0x2;           /* HRESET_REQ */
 169         }else{
 170         /*
 171          * Initiate hard reset in debug control register DBCR0
 172          * Make sure MSR[DE] = 1
 173          */
 174                 unsigned long val, msr;
 175
 176                 msr = mfmsr ();
 177                 msr |= MSR_DE;
 178                 mtmsr (msr);
 179
 180                 val = mfspr(DBCR0);
 181                 val |= 0x70000000;
 182                 mtspr(DBCR0,val);
 183         }
 184         return 1;
 185 }
 186
 187
 188 /*
 189  * Get timebase clock frequency
 190  */
 191 unsigned long get_tbclk (void)
 192 {
 193
 194         sys_info_t  sys_info;
 195
 196         get_sys_info(&sys_info);
 197         return ((sys_info.freqSystemBus + 7L) / 8L);
 198 }
 199
 200
 201 #if defined(CONFIG_WATCHDOG)
 202 void
 203 watchdog_reset(void)
 204 {
 205         int re_enable = disable_interrupts();
 206         reset_85xx_watchdog();
 207         if (re_enable) enable_interrupts();
 208 }
 209
 210 void
 211 reset_85xx_watchdog(void)
 212 {
 213         /*
 214          * Clear TSR(WIS) bit by writing 1
 215          */
 216         unsigned long val;
 217         val = mfspr(SPRN_TSR);
 218         val |= TSR_WIS;
 219         mtspr(SPRN_TSR, val);
 220 }
 221 #endif  /* CONFIG_WATCHDOG */
 222
 223 #if defined(CONFIG_DDR_ECC)
 224 void dma_init(void) {
 225         volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
 226
 227         dma->satr0 = 0x02c40000;
 228         dma->datr0 = 0x02c40000;
 229         dma->sr0 = 0xfffffff; /* clear any errors */
 230         asm("sync; isync; msync");
 231         return;
 232 }
 233
 234 uint dma_check(void) {
 235         volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
 236         volatile uint status = dma->sr0;
 237
 238         /* While the channel is busy, spin */
 239         while((status & 4) == 4) {
 240                 status = dma->sr0;
 241         }
 242
 243         /* clear MR0[CS] channel start bit */
 244         dma->mr0 &= 0x00000001;
 245         asm("sync;isync;msync");
 246
 247         if (status != 0) {
 248                 printf ("DMA Error: status = %x\n", status);
 249         }
 250         return status;
 251 }
 252
 253 int dma_xfer(void *dest, uint count, void *src) {
 254         volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
 255
 256         dma->dar0 = (uint) dest;
 257         dma->sar0 = (uint) src;
 258         dma->bcr0 = count;
 259         dma->mr0 = 0xf000004;
 260         asm("sync;isync;msync");
 261         dma->mr0 = 0xf000005;
 262         asm("sync;isync;msync");
 263         return dma_check();
 264 }
 265 #endif