cpu/mpc85xx/cpu.c

   1 /*
   2  * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
   3  * (C) Copyright 2002, 2003 Motorola Inc.
   4  * Xianghua Xiao (X.Xiao@motorola.com)
   5  *
   6  * (C) Copyright 2000
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <watchdog.h>
  30 #include <command.h>
  31 #include <asm/cache.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 struct cpu_type {
  36         char name[15];
  37         u32 soc_ver;
  38 };
  39
  40 #define CPU_TYPE_ENTRY(x) {#x, SVR_##x}
  41
  42 struct cpu_type cpu_type_list [] = {
  43         CPU_TYPE_ENTRY(8533),
  44         CPU_TYPE_ENTRY(8533_E),
  45         CPU_TYPE_ENTRY(8540),
  46         CPU_TYPE_ENTRY(8541),
  47         CPU_TYPE_ENTRY(8541_E),
  48         CPU_TYPE_ENTRY(8543),
  49         CPU_TYPE_ENTRY(8543_E),
  50         CPU_TYPE_ENTRY(8544),
  51         CPU_TYPE_ENTRY(8544_E),
  52         CPU_TYPE_ENTRY(8545),
  53         CPU_TYPE_ENTRY(8545_E),
  54         CPU_TYPE_ENTRY(8547_E),
  55         CPU_TYPE_ENTRY(8548),
  56         CPU_TYPE_ENTRY(8548_E),
  57         CPU_TYPE_ENTRY(8555),
  58         CPU_TYPE_ENTRY(8555_E),
  59         CPU_TYPE_ENTRY(8560),
  60         CPU_TYPE_ENTRY(8567),
  61         CPU_TYPE_ENTRY(8567_E),
  62         CPU_TYPE_ENTRY(8568),
  63         CPU_TYPE_ENTRY(8568_E),
  64         CPU_TYPE_ENTRY(8572),
  65         CPU_TYPE_ENTRY(8572_E),
  66 };
  67
  68 int checkcpu (void)
  69 {
  70         sys_info_t sysinfo;
  71         uint lcrr;              /* local bus clock ratio register */
  72         uint clkdiv;            /* clock divider portion of lcrr */
  73         uint pvr, svr;
  74         uint fam;
  75         uint ver;
  76         uint major, minor;
  77         int i;
  78         u32 ddr_ratio;
  79         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  80
  81         svr = get_svr();
  82         ver = SVR_SOC_VER(svr);
  83         major = SVR_MAJ(svr);
  84         minor = SVR_MIN(svr);
  85
  86         puts("CPU:   ");
  87
  88         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
  89                 if (cpu_type_list[i].soc_ver == ver) {
  90                         puts(cpu_type_list[i].name);
  91                         break;
  92                 }
  93
  94         if (i == ARRAY_SIZE(cpu_type_list))
  95                 puts("Unknown");
  96
  97         printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  98
  99         pvr = get_pvr();
 100         fam = PVR_FAM(pvr);
 101         ver = PVR_VER(pvr);
 102         major = PVR_MAJ(pvr);
 103         minor = PVR_MIN(pvr);
 104
 105         printf("Core:  ");
 106         switch (fam) {
 107         case PVR_FAM(PVR_85xx):
 108             puts("E500");
 109             break;
 110         default:
 111             puts("Unknown");
 112             break;
 113         }
 114         printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
 115
 116         get_sys_info(&sysinfo);
 117
 118         puts("Clock Configuration:\n");
 119         printf("       CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
 120         printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
 121
 122         ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
 123         switch (ddr_ratio) {
 124         case 0x0:
 125                 printf("       DDR:%4lu MHz (%lu MT/s data rate), ",
 126                 sysinfo.freqDDRBus / 2000000, sysinfo.freqDDRBus / 1000000);
 127                 break;
 128         case 0x7:
 129                 printf("       DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
 130                 sysinfo.freqDDRBus / 2000000, sysinfo.freqDDRBus / 1000000);
 131                 break;
 132         default:
 133                 printf("       DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
 134                 sysinfo.freqDDRBus / 2000000, sysinfo.freqDDRBus / 1000000);
 135                 break;
 136         }
 137
 138 #if defined(CFG_LBC_LCRR)
 139         lcrr = CFG_LBC_LCRR;
 140 #else
 141         {
 142             volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 143
 144             lcrr = lbc->lcrr;
 145         }
 146 #endif
 147         clkdiv = lcrr & 0x0f;
 148         if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
 149 #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
 150                 /*
 151                  * Yes, the entire PQ38 family use the same
 152                  * bit-representation for twice the clock divider values.
 153                  */
 154                  clkdiv *= 2;
 155 #endif
 156                 printf("LBC:%4lu MHz\n",
 157                        sysinfo.freqSystemBus / 1000000 / clkdiv);
 158         } else {
 159                 printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
 160         }
 161
 162 #ifdef CONFIG_CPM2
 163         printf("CPM:  %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
 164 #endif
 165
 166         puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");
 167
 168         return 0;
 169 }
 170
 171
 172 /* ------------------------------------------------------------------------- */
 173
 174 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 175 {
 176         uint pvr;
 177         uint ver;
 178         pvr = get_pvr();
 179         ver = PVR_VER(pvr);
 180         if (ver & 1){
 181         /* e500 v2 core has reset control register */
 182                 volatile unsigned int * rstcr;
 183                 rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
 184                 *rstcr = 0x2;           /* HRESET_REQ */
 185         }else{
 186         /*
 187          * Initiate hard reset in debug control register DBCR0
 188          * Make sure MSR[DE] = 1
 189          */
 190                 unsigned long val, msr;
 191
 192                 msr = mfmsr ();
 193                 msr |= MSR_DE;
 194                 mtmsr (msr);
 195
 196                 val = mfspr(DBCR0);
 197                 val |= 0x70000000;
 198                 mtspr(DBCR0,val);
 199         }
 200         return 1;
 201 }
 202
 203
 204 /*
 205  * Get timebase clock frequency
 206  */
 207 unsigned long get_tbclk (void)
 208 {
 209         return (gd->bus_clk + 4UL)/8UL;
 210 }
 211
 212
 213 #if defined(CONFIG_WATCHDOG)
 214 void
 215 watchdog_reset(void)
 216 {
 217         int re_enable = disable_interrupts();
 218         reset_85xx_watchdog();
 219         if (re_enable) enable_interrupts();
 220 }
 221
 222 void
 223 reset_85xx_watchdog(void)
 224 {
 225         /*
 226          * Clear TSR(WIS) bit by writing 1
 227          */
 228         unsigned long val;
 229         val = mfspr(SPRN_TSR);
 230         val |= TSR_WIS;
 231         mtspr(SPRN_TSR, val);
 232 }
 233 #endif  /* CONFIG_WATCHDOG */
 234
 235 #if defined(CONFIG_DDR_ECC)
 236 void dma_init(void) {
 237         volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
 238
 239         dma->satr0 = 0x02c40000;
 240         dma->datr0 = 0x02c40000;
 241         dma->sr0 = 0xfffffff; /* clear any errors */
 242         asm("sync; isync; msync");
 243         return;
 244 }
 245
 246 uint dma_check(void) {
 247         volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
 248         volatile uint status = dma->sr0;
 249
 250         /* While the channel is busy, spin */
 251         while((status & 4) == 4) {
 252                 status = dma->sr0;
 253         }
 254
 255         /* clear MR0[CS] channel start bit */
 256         dma->mr0 &= 0x00000001;
 257         asm("sync;isync;msync");
 258
 259         if (status != 0) {
 260                 printf ("DMA Error: status = %x\n", status);
 261         }
 262         return status;
 263 }
 264
 265 int dma_xfer(void *dest, uint count, void *src) {
 266         volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
 267
 268         dma->dar0 = (uint) dest;
 269         dma->sar0 = (uint) src;
 270         dma->bcr0 = count;
 271         dma->mr0 = 0xf000004;
 272         asm("sync;isync;msync");
 273         dma->mr0 = 0xf000005;
 274         asm("sync;isync;msync");
 275         return dma_check();
 276 }
 277 #endif