cpu/mpc85xx/cpu_init.c

   1 /*
   2  * Copyright 2007-2009 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2003 Motorola Inc.
   5  * Modified by Xianghua Xiao, X.Xiao@motorola.com
   6  *
   7  * (C) Copyright 2000
   8  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <watchdog.h>
  31 #include <asm/processor.h>
  32 #include <ioports.h>
  33 #include <asm/io.h>
  34 #include <asm/mmu.h>
  35 #include <asm/fsl_law.h>
  36 #include "mp.h"
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #ifdef CONFIG_MPC8536
  41 extern void fsl_serdes_init(void);
  42 #endif
  43
  44 #ifdef CONFIG_QE
  45 extern qe_iop_conf_t qe_iop_conf_tab[];
  46 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  47                                 int open_drain, int assign);
  48 extern void qe_init(uint qe_base);
  49 extern void qe_reset(void);
  50
  51 static void config_qe_ioports(void)
  52 {
  53         u8      port, pin;
  54         int     dir, open_drain, assign;
  55         int     i;
  56
  57         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  58                 port            = qe_iop_conf_tab[i].port;
  59                 pin             = qe_iop_conf_tab[i].pin;
  60                 dir             = qe_iop_conf_tab[i].dir;
  61                 open_drain      = qe_iop_conf_tab[i].open_drain;
  62                 assign          = qe_iop_conf_tab[i].assign;
  63                 qe_config_iopin(port, pin, dir, open_drain, assign);
  64         }
  65 }
  66 #endif
  67
  68 #ifdef CONFIG_CPM2
  69 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
  70 {
  71         int portnum;
  72
  73         for (portnum = 0; portnum < 4; portnum++) {
  74                 uint pmsk = 0,
  75                      ppar = 0,
  76                      psor = 0,
  77                      pdir = 0,
  78                      podr = 0,
  79                      pdat = 0;
  80                 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
  81                 iop_conf_t *eiopc = iopc + 32;
  82                 uint msk = 1;
  83
  84                 /*
  85                  * NOTE:
  86                  * index 0 refers to pin 31,
  87                  * index 31 refers to pin 0
  88                  */
  89                 while (iopc < eiopc) {
  90                         if (iopc->conf) {
  91                                 pmsk |= msk;
  92                                 if (iopc->ppar)
  93                                         ppar |= msk;
  94                                 if (iopc->psor)
  95                                         psor |= msk;
  96                                 if (iopc->pdir)
  97                                         pdir |= msk;
  98                                 if (iopc->podr)
  99                                         podr |= msk;
 100                                 if (iopc->pdat)
 101                                         pdat |= msk;
 102                         }
 103
 104                         msk <<= 1;
 105                         iopc++;
 106                 }
 107
 108                 if (pmsk != 0) {
 109                         volatile ioport_t *iop = ioport_addr (cpm, portnum);
 110                         uint tpmsk = ~pmsk;
 111
 112                         /*
 113                          * the (somewhat confused) paragraph at the
 114                          * bottom of page 35-5 warns that there might
 115                          * be "unknown behaviour" when programming
 116                          * PSORx and PDIRx, if PPARx = 1, so I
 117                          * decided this meant I had to disable the
 118                          * dedicated function first, and enable it
 119                          * last.
 120                          */
 121                         iop->ppar &= tpmsk;
 122                         iop->psor = (iop->psor & tpmsk) | psor;
 123                         iop->podr = (iop->podr & tpmsk) | podr;
 124                         iop->pdat = (iop->pdat & tpmsk) | pdat;
 125                         iop->pdir = (iop->pdir & tpmsk) | pdir;
 126                         iop->ppar |= ppar;
 127                 }
 128         }
 129 }
 130 #endif
 131
 132 /* We run cpu_init_early_f in AS = 1 */
 133 void cpu_init_early_f(void)
 134 {
 135         u32 mas0, mas1, mas2, mas3, mas7;
 136         int i;
 137
 138         /* Pointer is writable since we allocated a register for it */
 139         gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 140
 141         /*
 142          * Clear initial global data
 143          *   we don't use memset so we can share this code with NAND_SPL
 144          */
 145         for (i = 0; i < sizeof(gd_t); i++)
 146                 ((char *)gd)[i] = 0;
 147
 148         mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0);
 149         mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K);
 150         mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
 151         mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
 152         mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
 153
 154         write_tlb(mas0, mas1, mas2, mas3, mas7);
 155
 156         /* set up CCSR if we want it moved */
 157 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
 158         {
 159                 u32 temp;
 160                 volatile u32 *ccsr_virt =
 161                         (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
 162
 163                 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1);
 164                 /* mas1 is the same as above */
 165                 mas2 = FSL_BOOKE_MAS2((u32)ccsr_virt, MAS2_I|MAS2_G);
 166                 mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0,
 167                                                 MAS3_SW|MAS3_SR);
 168                 mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT);
 169
 170                 write_tlb(mas0, mas1, mas2, mas3, mas7);
 171
 172                 temp = in_be32(ccsr_virt);
 173                 out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
 174                 temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR);
 175         }
 176 #endif
 177
 178         init_laws();
 179         invalidate_tlb(0);
 180         init_tlbs();
 181 }
 182
 183 /*
 184  * Breathe some life into the CPU...
 185  *
 186  * Set up the memory map
 187  * initialize a bunch of registers
 188  */
 189
 190 void cpu_init_f (void)
 191 {
 192         volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 193         extern void m8560_cpm_reset (void);
 194 #ifdef CONFIG_MPC8548
 195         ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 196         uint svr = get_svr();
 197
 198         /*
 199          * CPU2 errata workaround: A core hang possible while executing
 200          * a msync instruction and a snoopable transaction from an I/O
 201          * master tagged to make quick forward progress is present.
 202          * Fixed in silicon rev 2.1.
 203          */
 204         if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
 205                 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
 206 #endif
 207
 208         disable_tlb(14);
 209         disable_tlb(15);
 210
 211 #ifdef CONFIG_CPM2
 212         config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
 213 #endif
 214
 215         /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 216          * addresses - these have to be modified later when FLASH size
 217          * has been determined
 218          */
 219 #if defined(CONFIG_SYS_OR0_REMAP)
 220         memctl->or0 = CONFIG_SYS_OR0_REMAP;
 221 #endif
 222 #if defined(CONFIG_SYS_OR1_REMAP)
 223         memctl->or1 = CONFIG_SYS_OR1_REMAP;
 224 #endif
 225
 226         /* now restrict to preliminary range */
 227         /* if cs1 is already set via debugger, leave cs0/cs1 alone */
 228         if (! memctl->br1 & 1) {
 229 #if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
 230                 memctl->br0 = CONFIG_SYS_BR0_PRELIM;
 231                 memctl->or0 = CONFIG_SYS_OR0_PRELIM;
 232 #endif
 233
 234 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
 235                 memctl->or1 = CONFIG_SYS_OR1_PRELIM;
 236                 memctl->br1 = CONFIG_SYS_BR1_PRELIM;
 237 #endif
 238         }
 239
 240 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
 241         memctl->or2 = CONFIG_SYS_OR2_PRELIM;
 242         memctl->br2 = CONFIG_SYS_BR2_PRELIM;
 243 #endif
 244
 245 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
 246         memctl->or3 = CONFIG_SYS_OR3_PRELIM;
 247         memctl->br3 = CONFIG_SYS_BR3_PRELIM;
 248 #endif
 249
 250 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
 251         memctl->or4 = CONFIG_SYS_OR4_PRELIM;
 252         memctl->br4 = CONFIG_SYS_BR4_PRELIM;
 253 #endif
 254
 255 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
 256         memctl->or5 = CONFIG_SYS_OR5_PRELIM;
 257         memctl->br5 = CONFIG_SYS_BR5_PRELIM;
 258 #endif
 259
 260 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
 261         memctl->or6 = CONFIG_SYS_OR6_PRELIM;
 262         memctl->br6 = CONFIG_SYS_BR6_PRELIM;
 263 #endif
 264
 265 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
 266         memctl->or7 = CONFIG_SYS_OR7_PRELIM;
 267         memctl->br7 = CONFIG_SYS_BR7_PRELIM;
 268 #endif
 269
 270 #if defined(CONFIG_CPM2)
 271         m8560_cpm_reset();
 272 #endif
 273 #ifdef CONFIG_QE
 274         /* Config QE ioports */
 275         config_qe_ioports();
 276 #endif
 277 #if defined(CONFIG_MPC8536)
 278         fsl_serdes_init();
 279 #endif
 280 #if defined(CONFIG_FSL_DMA)
 281         dma_init();
 282 #endif
 283 }
 284
 285
 286 /*
 287  * Initialize L2 as cache.
 288  *
 289  * The newer 8548, etc, parts have twice as much cache, but
 290  * use the same bit-encoding as the older 8555, etc, parts.
 291  *
 292  */
 293
 294 int cpu_init_r(void)
 295 {
 296         puts ("L2:    ");
 297
 298 #if defined(CONFIG_L2_CACHE)
 299         volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 300         volatile uint cache_ctl;
 301         uint svr, ver;
 302         uint l2srbar;
 303         u32 l2siz_field;
 304
 305         svr = get_svr();
 306         ver = SVR_SOC_VER(svr);
 307
 308         asm("msync;isync");
 309         cache_ctl = l2cache->l2ctl;
 310
 311 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
 312         if (cache_ctl & MPC85xx_L2CTL_L2E) {
 313                 /* Clear L2 SRAM memory-mapped base address */
 314                 out_be32(&l2cache->l2srbar0, 0x0);
 315                 out_be32(&l2cache->l2srbar1, 0x0);
 316
 317                 /* set MBECCDIS=0, SBECCDIS=0 */
 318                 clrbits_be32(&l2cache->l2errdis,
 319                                 (MPC85xx_L2ERRDIS_MBECC |
 320                                  MPC85xx_L2ERRDIS_SBECC));
 321
 322                 /* set L2E=0, L2SRAM=0 */
 323                 clrbits_be32(&l2cache->l2ctl,
 324                                 (MPC85xx_L2CTL_L2E |
 325                                  MPC85xx_L2CTL_L2SRAM_ENTIRE));
 326         }
 327 #endif
 328
 329         l2siz_field = (cache_ctl >> 28) & 0x3;
 330
 331         switch (l2siz_field) {
 332         case 0x0:
 333                 printf(" unknown size (0x%08x)\n", cache_ctl);
 334                 return -1;
 335                 break;
 336         case 0x1:
 337                 if (ver == SVR_8540 || ver == SVR_8560   ||
 338                     ver == SVR_8541 || ver == SVR_8541_E ||
 339                     ver == SVR_8555 || ver == SVR_8555_E) {
 340                         puts("128 KB ");
 341                         /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
 342                         cache_ctl = 0xc4000000;
 343                 } else {
 344                         puts("256 KB ");
 345                         cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
 346                 }
 347                 break;
 348         case 0x2:
 349                 if (ver == SVR_8540 || ver == SVR_8560   ||
 350                     ver == SVR_8541 || ver == SVR_8541_E ||
 351                     ver == SVR_8555 || ver == SVR_8555_E) {
 352                         puts("256 KB ");
 353                         /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
 354                         cache_ctl = 0xc8000000;
 355                 } else {
 356                         puts ("512 KB ");
 357                         /* set L2E=1, L2I=1, & L2SRAM=0 */
 358                         cache_ctl = 0xc0000000;
 359                 }
 360                 break;
 361         case 0x3:
 362                 puts("1024 KB ");
 363                 /* set L2E=1, L2I=1, & L2SRAM=0 */
 364                 cache_ctl = 0xc0000000;
 365                 break;
 366         }
 367
 368         if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
 369                 puts("already enabled");
 370                 l2srbar = l2cache->l2srbar0;
 371 #ifdef CONFIG_SYS_INIT_L2_ADDR
 372                 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
 373                                 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
 374                         l2srbar = CONFIG_SYS_INIT_L2_ADDR;
 375                         l2cache->l2srbar0 = l2srbar;
 376                         printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
 377                 }
 378 #endif /* CONFIG_SYS_INIT_L2_ADDR */
 379                 puts("\n");
 380         } else {
 381                 asm("msync;isync");
 382                 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
 383                 asm("msync;isync");
 384                 puts("enabled\n");
 385         }
 386 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
 387         u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 388
 389         /* invalidate the L2 cache */
 390         mtspr(SPRN_L2CSR0, L2CSR0_L2FI);
 391         while (mfspr(SPRN_L2CSR0) & L2CSR0_L2FI)
 392                 ;
 393
 394         /* enable the cache */
 395         mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
 396
 397         if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E)
 398                 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
 399 #else
 400         puts("disabled\n");
 401 #endif
 402 #ifdef CONFIG_QE
 403         uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
 404         qe_init(qe_base);
 405         qe_reset();
 406 #endif
 407
 408 #if defined(CONFIG_MP)
 409         setup_mp();
 410 #endif
 411         return 0;
 412 }
 413
 414 extern void setup_ivors(void);
 415
 416 void arch_preboot_os(void)
 417 {
 418         setup_ivors();
 419 }