cpu/mpc85xx/cpu_init.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor.
   3  *
   4  * (C) Copyright 2003 Motorola Inc.
   5  * Modified by Xianghua Xiao, X.Xiao@motorola.com
   6  *
   7  * (C) Copyright 2000
   8  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <watchdog.h>
  31 #include <asm/processor.h>
  32 #include <ioports.h>
  33 #include <asm/io.h>
  34 #include <asm/mmu.h>
  35 #include <asm/fsl_law.h>
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #ifdef CONFIG_QE
  40 extern qe_iop_conf_t qe_iop_conf_tab[];
  41 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  42                                 int open_drain, int assign);
  43 extern void qe_init(uint qe_base);
  44 extern void qe_reset(void);
  45
  46 static void config_qe_ioports(void)
  47 {
  48         u8      port, pin;
  49         int     dir, open_drain, assign;
  50         int     i;
  51
  52         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  53                 port            = qe_iop_conf_tab[i].port;
  54                 pin             = qe_iop_conf_tab[i].pin;
  55                 dir             = qe_iop_conf_tab[i].dir;
  56                 open_drain      = qe_iop_conf_tab[i].open_drain;
  57                 assign          = qe_iop_conf_tab[i].assign;
  58                 qe_config_iopin(port, pin, dir, open_drain, assign);
  59         }
  60 }
  61 #endif
  62
  63 #ifdef CONFIG_CPM2
  64 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
  65 {
  66         int portnum;
  67
  68         for (portnum = 0; portnum < 4; portnum++) {
  69                 uint pmsk = 0,
  70                      ppar = 0,
  71                      psor = 0,
  72                      pdir = 0,
  73                      podr = 0,
  74                      pdat = 0;
  75                 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
  76                 iop_conf_t *eiopc = iopc + 32;
  77                 uint msk = 1;
  78
  79                 /*
  80                  * NOTE:
  81                  * index 0 refers to pin 31,
  82                  * index 31 refers to pin 0
  83                  */
  84                 while (iopc < eiopc) {
  85                         if (iopc->conf) {
  86                                 pmsk |= msk;
  87                                 if (iopc->ppar)
  88                                         ppar |= msk;
  89                                 if (iopc->psor)
  90                                         psor |= msk;
  91                                 if (iopc->pdir)
  92                                         pdir |= msk;
  93                                 if (iopc->podr)
  94                                         podr |= msk;
  95                                 if (iopc->pdat)
  96                                         pdat |= msk;
  97                         }
  98
  99                         msk <<= 1;
 100                         iopc++;
 101                 }
 102
 103                 if (pmsk != 0) {
 104                         volatile ioport_t *iop = ioport_addr (cpm, portnum);
 105                         uint tpmsk = ~pmsk;
 106
 107                         /*
 108                          * the (somewhat confused) paragraph at the
 109                          * bottom of page 35-5 warns that there might
 110                          * be "unknown behaviour" when programming
 111                          * PSORx and PDIRx, if PPARx = 1, so I
 112                          * decided this meant I had to disable the
 113                          * dedicated function first, and enable it
 114                          * last.
 115                          */
 116                         iop->ppar &= tpmsk;
 117                         iop->psor = (iop->psor & tpmsk) | psor;
 118                         iop->podr = (iop->podr & tpmsk) | podr;
 119                         iop->pdat = (iop->pdat & tpmsk) | pdat;
 120                         iop->pdir = (iop->pdir & tpmsk) | pdir;
 121                         iop->ppar |= ppar;
 122                 }
 123         }
 124 }
 125 #endif
 126
 127 /* We run cpu_init_early_f in AS = 1 */
 128 void cpu_init_early_f(void)
 129 {
 130         set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR,
 131                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 132                 1, 0, BOOKE_PAGESZ_4K, 0);
 133
 134         /* set up CCSR if we want it moved */
 135 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
 136         {
 137                 u32 temp;
 138
 139                 set_tlb(0, CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_DEFAULT,
 140                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 141                         1, 1, BOOKE_PAGESZ_4K, 0);
 142
 143                 temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT);
 144                 out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR >> 12);
 145
 146                 temp = in_be32((volatile u32 *)CFG_CCSRBAR);
 147         }
 148 #endif
 149
 150         init_laws();
 151         invalidate_tlb(0);
 152         init_tlbs();
 153 }
 154
 155 /*
 156  * Breathe some life into the CPU...
 157  *
 158  * Set up the memory map
 159  * initialize a bunch of registers
 160  */
 161
 162 void cpu_init_f (void)
 163 {
 164         volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
 165         extern void m8560_cpm_reset (void);
 166
 167         disable_tlb(14);
 168         disable_tlb(15);
 169
 170         /* Pointer is writable since we allocated a register for it */
 171         gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
 172
 173         /* Clear initial global data */
 174         memset ((void *) gd, 0, sizeof (gd_t));
 175
 176 #ifdef CONFIG_CPM2
 177         config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR);
 178 #endif
 179
 180         /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 181          * addresses - these have to be modified later when FLASH size
 182          * has been determined
 183          */
 184 #if defined(CFG_OR0_REMAP)
 185         memctl->or0 = CFG_OR0_REMAP;
 186 #endif
 187 #if defined(CFG_OR1_REMAP)
 188         memctl->or1 = CFG_OR1_REMAP;
 189 #endif
 190
 191         /* now restrict to preliminary range */
 192         /* if cs1 is already set via debugger, leave cs0/cs1 alone */
 193         if (! memctl->br1 & 1) {
 194 #if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
 195                 memctl->br0 = CFG_BR0_PRELIM;
 196                 memctl->or0 = CFG_OR0_PRELIM;
 197 #endif
 198
 199 #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
 200                 memctl->or1 = CFG_OR1_PRELIM;
 201                 memctl->br1 = CFG_BR1_PRELIM;
 202 #endif
 203         }
 204
 205 #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
 206         memctl->or2 = CFG_OR2_PRELIM;
 207         memctl->br2 = CFG_BR2_PRELIM;
 208 #endif
 209
 210 #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
 211         memctl->or3 = CFG_OR3_PRELIM;
 212         memctl->br3 = CFG_BR3_PRELIM;
 213 #endif
 214
 215 #if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
 216         memctl->or4 = CFG_OR4_PRELIM;
 217         memctl->br4 = CFG_BR4_PRELIM;
 218 #endif
 219
 220 #if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
 221         memctl->or5 = CFG_OR5_PRELIM;
 222         memctl->br5 = CFG_BR5_PRELIM;
 223 #endif
 224
 225 #if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
 226         memctl->or6 = CFG_OR6_PRELIM;
 227         memctl->br6 = CFG_BR6_PRELIM;
 228 #endif
 229
 230 #if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
 231         memctl->or7 = CFG_OR7_PRELIM;
 232         memctl->br7 = CFG_BR7_PRELIM;
 233 #endif
 234
 235 #if defined(CONFIG_CPM2)
 236         m8560_cpm_reset();
 237 #endif
 238 #ifdef CONFIG_QE
 239         /* Config QE ioports */
 240         config_qe_ioports();
 241 #endif
 242
 243 }
 244
 245
 246 /*
 247  * Initialize L2 as cache.
 248  *
 249  * The newer 8548, etc, parts have twice as much cache, but
 250  * use the same bit-encoding as the older 8555, etc, parts.
 251  *
 252  */
 253
 254 int cpu_init_r(void)
 255 {
 256 #ifdef CONFIG_CLEAR_LAW0
 257 #ifdef CONFIG_FSL_LAW
 258         disable_law(0);
 259 #else
 260         volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
 261
 262         /* clear alternate boot location LAW (used for sdram, or ddr bank) */
 263         ecm->lawar0 = 0;
 264 #endif
 265 #endif
 266
 267 #if defined(CONFIG_L2_CACHE)
 268         volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
 269         volatile uint cache_ctl;
 270         uint svr, ver;
 271         uint l2srbar;
 272
 273         svr = get_svr();
 274         ver = SVR_VER(svr);
 275
 276         asm("msync;isync");
 277         cache_ctl = l2cache->l2ctl;
 278
 279         switch (cache_ctl & 0x30000000) {
 280         case 0x20000000:
 281                 if (ver == SVR_8548 || ver == SVR_8548_E ||
 282                     ver == SVR_8544 || ver == SVR_8568_E) {
 283                         printf ("L2 cache 512KB:");
 284                         /* set L2E=1, L2I=1, & L2SRAM=0 */
 285                         cache_ctl = 0xc0000000;
 286                 } else {
 287                         printf ("L2 cache 256KB:");
 288                         /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
 289                         cache_ctl = 0xc8000000;
 290                 }
 291                 break;
 292         case 0x10000000:
 293                 printf ("L2 cache 256KB:");
 294                 if (ver == SVR_8544 || ver == SVR_8544_E) {
 295                         cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
 296                 }
 297                 break;
 298         case 0x30000000:
 299         case 0x00000000:
 300         default:
 301                 printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
 302                 return -1;
 303         }
 304
 305         if (l2cache->l2ctl & 0x80000000) {
 306                 printf(" already enabled.");
 307                 l2srbar = l2cache->l2srbar0;
 308 #ifdef CFG_INIT_L2_ADDR
 309                 if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) {
 310                         l2srbar = CFG_INIT_L2_ADDR;
 311                         l2cache->l2srbar0 = l2srbar;
 312                         printf("  Moving to 0x%08x", CFG_INIT_L2_ADDR);
 313                 }
 314 #endif /* CFG_INIT_L2_ADDR */
 315                 puts("\n");
 316         } else {
 317                 asm("msync;isync");
 318                 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
 319                 asm("msync;isync");
 320                 printf(" enabled\n");
 321         }
 322 #else
 323         printf("L2 cache: disabled\n");
 324 #endif
 325 #ifdef CONFIG_QE
 326         uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */
 327         qe_init(qe_base);
 328         qe_reset();
 329 #endif
 330
 331         return 0;
 332 }