cpu/mpc85xx/cpu_init.c

   1 /*
   2  * (C) Copyright 2003 Motorola Inc.
   3  * Modified by Xianghua Xiao, X.Xiao@motorola.com
   4  *
   5  * (C) Copyright 2000
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <watchdog.h>
  29 #include <asm/processor.h>
  30 #include <ioports.h>
  31 #include <asm/io.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #ifdef CONFIG_CPM2
  36 static void config_8560_ioports (volatile immap_t * immr)
  37 {
  38         int portnum;
  39
  40         for (portnum = 0; portnum < 4; portnum++) {
  41                 uint pmsk = 0,
  42                      ppar = 0,
  43                      psor = 0,
  44                      pdir = 0,
  45                      podr = 0,
  46                      pdat = 0;
  47                 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
  48                 iop_conf_t *eiopc = iopc + 32;
  49                 uint msk = 1;
  50
  51                 /*
  52                  * NOTE:
  53                  * index 0 refers to pin 31,
  54                  * index 31 refers to pin 0
  55                  */
  56                 while (iopc < eiopc) {
  57                         if (iopc->conf) {
  58                                 pmsk |= msk;
  59                                 if (iopc->ppar)
  60                                         ppar |= msk;
  61                                 if (iopc->psor)
  62                                         psor |= msk;
  63                                 if (iopc->pdir)
  64                                         pdir |= msk;
  65                                 if (iopc->podr)
  66                                         podr |= msk;
  67                                 if (iopc->pdat)
  68                                         pdat |= msk;
  69                         }
  70
  71                         msk <<= 1;
  72                         iopc++;
  73                 }
  74
  75                 if (pmsk != 0) {
  76                         volatile ioport_t *iop = ioport_addr (immr, portnum);
  77                         uint tpmsk = ~pmsk;
  78
  79                         /*
  80                          * the (somewhat confused) paragraph at the
  81                          * bottom of page 35-5 warns that there might
  82                          * be "unknown behaviour" when programming
  83                          * PSORx and PDIRx, if PPARx = 1, so I
  84                          * decided this meant I had to disable the
  85                          * dedicated function first, and enable it
  86                          * last.
  87                          */
  88                         iop->ppar &= tpmsk;
  89                         iop->psor = (iop->psor & tpmsk) | psor;
  90                         iop->podr = (iop->podr & tpmsk) | podr;
  91                         iop->pdat = (iop->pdat & tpmsk) | pdat;
  92                         iop->pdir = (iop->pdir & tpmsk) | pdir;
  93                         iop->ppar |= ppar;
  94                 }
  95         }
  96 }
  97 #endif
  98
  99 /*
 100  * Breathe some life into the CPU...
 101  *
 102  * Set up the memory map
 103  * initialize a bunch of registers
 104  */
 105
 106 void cpu_init_f (void)
 107 {
 108         volatile immap_t    *immap = (immap_t *)CFG_IMMR;
 109         volatile ccsr_lbc_t *memctl = &immap->im_lbc;
 110         extern void m8560_cpm_reset (void);
 111
 112         /* Pointer is writable since we allocated a register for it */
 113         gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
 114
 115         /* Clear initial global data */
 116         memset ((void *) gd, 0, sizeof (gd_t));
 117
 118
 119 #ifdef CONFIG_CPM2
 120         config_8560_ioports(immap);
 121 #endif
 122
 123         /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 124          * addresses - these have to be modified later when FLASH size
 125          * has been determined
 126          */
 127 #if defined(CFG_OR0_REMAP)
 128         memctl->or0 = CFG_OR0_REMAP;
 129 #endif
 130 #if defined(CFG_OR1_REMAP)
 131         memctl->or1 = CFG_OR1_REMAP;
 132 #endif
 133
 134         /* now restrict to preliminary range */
 135 #if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
 136         memctl->br0 = CFG_BR0_PRELIM;
 137         memctl->or0 = CFG_OR0_PRELIM;
 138 #endif
 139
 140 #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
 141         memctl->or1 = CFG_OR1_PRELIM;
 142         memctl->br1 = CFG_BR1_PRELIM;
 143 #endif
 144
 145 #if !defined(CONFIG_MPC85xx)
 146 #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
 147         memctl->or2 = CFG_OR2_PRELIM;
 148         memctl->br2 = CFG_BR2_PRELIM;
 149 #endif
 150 #endif
 151
 152 #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
 153         memctl->or3 = CFG_OR3_PRELIM;
 154         memctl->br3 = CFG_BR3_PRELIM;
 155 #endif
 156
 157 #if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
 158         memctl->or4 = CFG_OR4_PRELIM;
 159         memctl->br4 = CFG_BR4_PRELIM;
 160 #endif
 161
 162 #if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
 163         memctl->or5 = CFG_OR5_PRELIM;
 164         memctl->br5 = CFG_BR5_PRELIM;
 165 #endif
 166
 167 #if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
 168         memctl->or6 = CFG_OR6_PRELIM;
 169         memctl->br6 = CFG_BR6_PRELIM;
 170 #endif
 171
 172 #if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
 173         memctl->or7 = CFG_OR7_PRELIM;
 174         memctl->br7 = CFG_BR7_PRELIM;
 175 #endif
 176
 177 #if defined(CONFIG_CPM2)
 178         m8560_cpm_reset();
 179 #endif
 180 }
 181
 182
 183 /*
 184  * Initialize L2 as cache.
 185  *
 186  * The newer 8548, etc, parts have twice as much cache, but
 187  * use the same bit-encoding as the older 8555, etc, parts.
 188  *
 189  * FIXME: Use PVR_VER(pvr) == 1 test here instead of SVR_VER()?
 190  */
 191
 192 int cpu_init_r(void)
 193 {
 194 #if defined(CONFIG_L2_CACHE)
 195         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 196         volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
 197         volatile uint cache_ctl;
 198         uint svr, ver;
 199
 200         svr = get_svr();
 201         ver = SVR_VER(svr);
 202
 203         asm("msync;isync");
 204         cache_ctl = l2cache->l2ctl;
 205
 206         switch (cache_ctl & 0x30000000) {
 207         case 0x20000000:
 208                 if (ver == SVR_8548 || ver == SVR_8548_E) {
 209                         printf ("L2 cache 512KB:");
 210                 } else {
 211                         printf ("L2 cache 256KB:");
 212                 }
 213                 break;
 214         case 0x00000000:
 215         case 0x10000000:
 216         case 0x30000000:
 217         default:
 218                 printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
 219                 return -1;
 220         }
 221
 222         asm("msync;isync");
 223         l2cache->l2ctl = 0x68000000; /* invalidate */
 224         cache_ctl = l2cache->l2ctl;
 225         asm("msync;isync");
 226
 227         l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */
 228         cache_ctl = l2cache->l2ctl;
 229         asm("msync;isync");
 230
 231         printf(" enabled\n");
 232 #else
 233         printf("L2 cache: disabled\n");
 234 #endif
 235
 236         return 0;
 237 }