2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
11 #include <asm/fsl_ddr_sdram.h>
13 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
14 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
17 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t
*regs
,
18 unsigned int ctrl_num
)
21 volatile ccsr_ddr_t
*ddr
;
26 ddr
= (void *)CONFIG_SYS_MPC85xx_DDR_ADDR
;
29 ddr
= (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR
;
32 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__
, ctrl_num
);
36 for (i
= 0; i
< CONFIG_CHIP_SELECTS_PER_CTRL
; i
++) {
38 out_be32(&ddr
->cs0_bnds
, regs
->cs
[i
].bnds
);
39 out_be32(&ddr
->cs0_config
, regs
->cs
[i
].config
);
40 out_be32(&ddr
->cs0_config_2
, regs
->cs
[i
].config_2
);
43 out_be32(&ddr
->cs1_bnds
, regs
->cs
[i
].bnds
);
44 out_be32(&ddr
->cs1_config
, regs
->cs
[i
].config
);
45 out_be32(&ddr
->cs1_config_2
, regs
->cs
[i
].config_2
);
48 out_be32(&ddr
->cs2_bnds
, regs
->cs
[i
].bnds
);
49 out_be32(&ddr
->cs2_config
, regs
->cs
[i
].config
);
50 out_be32(&ddr
->cs2_config_2
, regs
->cs
[i
].config_2
);
53 out_be32(&ddr
->cs3_bnds
, regs
->cs
[i
].bnds
);
54 out_be32(&ddr
->cs3_config
, regs
->cs
[i
].config
);
55 out_be32(&ddr
->cs3_config_2
, regs
->cs
[i
].config_2
);
59 out_be32(&ddr
->timing_cfg_3
, regs
->timing_cfg_3
);
60 out_be32(&ddr
->timing_cfg_0
, regs
->timing_cfg_0
);
61 out_be32(&ddr
->timing_cfg_1
, regs
->timing_cfg_1
);
62 out_be32(&ddr
->timing_cfg_2
, regs
->timing_cfg_2
);
63 out_be32(&ddr
->sdram_cfg_2
, regs
->ddr_sdram_cfg_2
);
64 out_be32(&ddr
->sdram_mode
, regs
->ddr_sdram_mode
);
65 out_be32(&ddr
->sdram_mode_2
, regs
->ddr_sdram_mode_2
);
66 out_be32(&ddr
->sdram_md_cntl
, regs
->ddr_sdram_md_cntl
);
67 out_be32(&ddr
->sdram_interval
, regs
->ddr_sdram_interval
);
68 out_be32(&ddr
->sdram_data_init
, regs
->ddr_data_init
);
69 out_be32(&ddr
->sdram_clk_cntl
, regs
->ddr_sdram_clk_cntl
);
70 out_be32(&ddr
->init_addr
, regs
->ddr_init_addr
);
71 out_be32(&ddr
->init_ext_addr
, regs
->ddr_init_ext_addr
);
73 out_be32(&ddr
->timing_cfg_4
, regs
->timing_cfg_4
);
74 out_be32(&ddr
->timing_cfg_5
, regs
->timing_cfg_5
);
75 out_be32(&ddr
->ddr_zq_cntl
, regs
->ddr_zq_cntl
);
76 out_be32(&ddr
->ddr_wrlvl_cntl
, regs
->ddr_wrlvl_cntl
);
77 out_be32(&ddr
->ddr_pd_cntl
, regs
->ddr_pd_cntl
);
78 out_be32(&ddr
->ddr_sr_cntr
, regs
->ddr_sr_cntr
);
79 out_be32(&ddr
->ddr_sdram_rcw_1
, regs
->ddr_sdram_rcw_1
);
80 out_be32(&ddr
->ddr_sdram_rcw_2
, regs
->ddr_sdram_rcw_2
);
82 /* Set, but do not enable the memory */
83 temp_sdram_cfg
= regs
->ddr_sdram_cfg
;
84 temp_sdram_cfg
&= ~(SDRAM_CFG_MEM_EN
);
85 out_be32(&ddr
->sdram_cfg
, temp_sdram_cfg
);
87 * For 8572 DDR1 erratum - DDR controller may enter illegal state
88 * when operatiing in 32-bit bus mode with 4-beat bursts,
89 * This erratum does not affect DDR3 mode, only for DDR2 mode.
92 if ((((in_be32(&ddr
->sdram_cfg
) >> 24) & 0x7) == SDRAM_TYPE_DDR2
)
93 && in_be32(&ddr
->sdram_cfg
) & 0x80000) {
95 u32 temp
= in_be32(&ddr
->debug_1
);
96 out_be32(&ddr
->debug_1
, temp
| 1);
101 * 200 painful micro-seconds must elapse between
102 * the DDR clock setup and the DDR config enable.
105 asm volatile("sync;isync");
107 /* Let the controller go */
108 temp_sdram_cfg
= in_be32(&ddr
->sdram_cfg
);
109 out_be32(&ddr
->sdram_cfg
, temp_sdram_cfg
| SDRAM_CFG_MEM_EN
);
111 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
112 while (in_be32(&ddr
->sdram_cfg_2
) & 0x10) {
113 udelay(10000); /* throttle polling rate */