2 * Copyright 2007-2009 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <fdt_support.h>
29 #include <asm/processor.h>
30 #include <linux/ctype.h>
31 #ifdef CONFIG_FSL_ESDHC
32 #include <fsl_esdhc.h>
35 DECLARE_GLOBAL_DATA_PTR
;
37 extern void ft_qe_setup(void *blob
);
38 extern void ft_fixup_num_cores(void *blob
);
43 void ft_fixup_cpu(void *blob
, u64 memory_limit
)
46 ulong spin_tbl_addr
= get_spin_phys_addr();
47 u32 bootpg
= determine_mp_bootpg();
50 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
51 while (off
!= -FDT_ERR_NOTFOUND
) {
52 u32
*reg
= (u32
*)fdt_getprop(blob
, off
, "reg", 0);
56 fdt_setprop_string(blob
, off
, "status", "okay");
58 u64 val
= *reg
* SIZE_BOOT_ENTRY
+ spin_tbl_addr
;
59 val
= cpu_to_fdt32(val
);
60 fdt_setprop_string(blob
, off
, "status",
62 fdt_setprop_string(blob
, off
, "enable-method",
64 fdt_setprop(blob
, off
, "cpu-release-addr",
68 printf ("cpu NULL\n");
70 off
= fdt_node_offset_by_prop_value(blob
, off
,
71 "device_type", "cpu", 4);
74 /* Reserve the boot page so OSes dont use it */
75 if ((u64
)bootpg
< memory_limit
) {
76 off
= fdt_add_mem_rsv(blob
, bootpg
, (u64
)4096);
78 printf("%s: %s\n", __FUNCTION__
, fdt_strerror(off
));
83 #define ft_fixup_l3cache(x, y)
85 #if defined(CONFIG_L2_CACHE)
86 /* return size in kilobytes */
87 static inline u32
l2cache_size(void)
89 volatile ccsr_l2cache_t
*l2cache
= (void *)CONFIG_SYS_MPC85xx_L2_ADDR
;
90 volatile u32 l2siz_field
= (l2cache
->l2ctl
>> 28) & 0x3;
91 u32 ver
= SVR_SOC_VER(get_svr());
93 switch (l2siz_field
) {
97 if (ver
== SVR_8540
|| ver
== SVR_8560
||
98 ver
== SVR_8541
|| ver
== SVR_8541_E
||
99 ver
== SVR_8555
|| ver
== SVR_8555_E
)
105 if (ver
== SVR_8540
|| ver
== SVR_8560
||
106 ver
== SVR_8541
|| ver
== SVR_8541_E
||
107 ver
== SVR_8555
|| ver
== SVR_8555_E
)
120 static inline void ft_fixup_l2cache(void *blob
)
124 struct cpu_type
*cpu
= identify_cpu(SVR_SOC_VER(get_svr()));
127 const u32 line_size
= 32;
128 const u32 num_ways
= 8;
129 const u32 size
= l2cache_size() * 1024;
130 const u32 num_sets
= size
/ (line_size
* num_ways
);
132 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
134 debug("no cpu node fount\n");
138 ph
= (u32
*)fdt_getprop(blob
, off
, "next-level-cache", 0);
141 debug("no next-level-cache property\n");
145 off
= fdt_node_offset_by_phandle(blob
, *ph
);
147 printf("%s: %s\n", __func__
, fdt_strerror(off
));
152 if (isdigit(cpu
->name
[0]))
153 len
= sprintf(compat_buf
,
154 "fsl,mpc%s-l2-cache-controller", cpu
->name
);
156 len
= sprintf(compat_buf
,
157 "fsl,%c%s-l2-cache-controller",
158 tolower(cpu
->name
[0]), cpu
->name
+ 1);
160 sprintf(&compat_buf
[len
+ 1], "cache");
162 fdt_setprop(blob
, off
, "cache-unified", NULL
, 0);
163 fdt_setprop_cell(blob
, off
, "cache-block-size", line_size
);
164 fdt_setprop_cell(blob
, off
, "cache-size", size
);
165 fdt_setprop_cell(blob
, off
, "cache-sets", num_sets
);
166 fdt_setprop_cell(blob
, off
, "cache-level", 2);
167 fdt_setprop(blob
, off
, "compatible", compat_buf
, sizeof(compat_buf
));
169 /* we dont bother w/L3 since no platform of this type has one */
171 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
172 static inline void ft_fixup_l2cache(void *blob
)
174 int off
, l2_off
, l3_off
= -1;
176 u32 l2cfg0
= mfspr(SPRN_L2CFG0
);
177 u32 size
, line_size
, num_ways
, num_sets
;
179 size
= (l2cfg0
& 0x3fff) * 64 * 1024;
180 num_ways
= ((l2cfg0
>> 14) & 0x1f) + 1;
181 line_size
= (((l2cfg0
>> 23) & 0x3) + 1) * 32;
182 num_sets
= size
/ (line_size
* num_ways
);
184 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
186 while (off
!= -FDT_ERR_NOTFOUND
) {
187 ph
= (u32
*)fdt_getprop(blob
, off
, "next-level-cache", 0);
190 debug("no next-level-cache property\n");
194 l2_off
= fdt_node_offset_by_phandle(blob
, *ph
);
196 printf("%s: %s\n", __func__
, fdt_strerror(off
));
200 fdt_setprop(blob
, l2_off
, "cache-unified", NULL
, 0);
201 fdt_setprop_cell(blob
, l2_off
, "cache-block-size", line_size
);
202 fdt_setprop_cell(blob
, l2_off
, "cache-size", size
);
203 fdt_setprop_cell(blob
, l2_off
, "cache-sets", num_sets
);
204 fdt_setprop_cell(blob
, l2_off
, "cache-level", 2);
205 fdt_setprop(blob
, l2_off
, "compatible", "cache", 6);
208 ph
= (u32
*)fdt_getprop(blob
, l2_off
, "next-level-cache", 0);
211 debug("no next-level-cache property\n");
217 off
= fdt_node_offset_by_prop_value(blob
, off
,
218 "device_type", "cpu", 4);
221 l3_off
= fdt_node_offset_by_phandle(blob
, l3_off
);
223 printf("%s: %s\n", __func__
, fdt_strerror(off
));
226 ft_fixup_l3cache(blob
, l3_off
);
230 #define ft_fixup_l2cache(x)
233 static inline void ft_fixup_cache(void *blob
)
237 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
239 while (off
!= -FDT_ERR_NOTFOUND
) {
240 u32 l1cfg0
= mfspr(SPRN_L1CFG0
);
241 u32 l1cfg1
= mfspr(SPRN_L1CFG1
);
242 u32 isize
, iline_size
, inum_sets
, inum_ways
;
243 u32 dsize
, dline_size
, dnum_sets
, dnum_ways
;
246 dsize
= (l1cfg0
& 0x7ff) * 1024;
247 dnum_ways
= ((l1cfg0
>> 11) & 0xff) + 1;
248 dline_size
= (((l1cfg0
>> 23) & 0x3) + 1) * 32;
249 dnum_sets
= dsize
/ (dline_size
* dnum_ways
);
251 fdt_setprop_cell(blob
, off
, "d-cache-block-size", dline_size
);
252 fdt_setprop_cell(blob
, off
, "d-cache-size", dsize
);
253 fdt_setprop_cell(blob
, off
, "d-cache-sets", dnum_sets
);
256 isize
= (l1cfg1
& 0x7ff) * 1024;
257 inum_ways
= ((l1cfg1
>> 11) & 0xff) + 1;
258 iline_size
= (((l1cfg1
>> 23) & 0x3) + 1) * 32;
259 inum_sets
= isize
/ (iline_size
* inum_ways
);
261 fdt_setprop_cell(blob
, off
, "i-cache-block-size", iline_size
);
262 fdt_setprop_cell(blob
, off
, "i-cache-size", isize
);
263 fdt_setprop_cell(blob
, off
, "i-cache-sets", inum_sets
);
265 off
= fdt_node_offset_by_prop_value(blob
, off
,
266 "device_type", "cpu", 4);
269 ft_fixup_l2cache(blob
);
273 void fdt_add_enet_stashing(void *fdt
)
275 do_fixup_by_compat(fdt
, "gianfar", "bd-stash", NULL
, 0, 1);
277 do_fixup_by_compat_u32(fdt
, "gianfar", "rx-stash-len", 96, 1);
279 do_fixup_by_compat_u32(fdt
, "gianfar", "rx-stash-idx", 0, 1);
282 void ft_cpu_setup(void *blob
, bd_t
*bd
)
288 /* delete crypto node if not on an E-processor */
289 if (!IS_E_PROCESSOR(get_svr()))
290 fdt_fixup_crypto_node(blob
, 0);
292 fdt_fixup_ethernet(blob
);
294 fdt_add_enet_stashing(blob
);
296 do_fixup_by_prop_u32(blob
, "device_type", "cpu", 4,
297 "timebase-frequency", get_tbclk(), 1);
298 do_fixup_by_prop_u32(blob
, "device_type", "cpu", 4,
299 "bus-frequency", bd
->bi_busfreq
, 1);
300 get_sys_info(&sysinfo
);
301 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
302 while (off
!= -FDT_ERR_NOTFOUND
) {
303 u32
*reg
= (u32
*)fdt_getprop(blob
, off
, "reg", 0);
304 val
= cpu_to_fdt32(sysinfo
.freqProcessor
[*reg
]);
305 fdt_setprop(blob
, off
, "clock-frequency", &val
, 4);
306 off
= fdt_node_offset_by_prop_value(blob
, off
, "device_type",
309 do_fixup_by_prop_u32(blob
, "device_type", "soc", 4,
310 "bus-frequency", bd
->bi_busfreq
, 1);
312 do_fixup_by_compat_u32(blob
, "fsl,pq3-localbus",
313 "bus-frequency", gd
->lbc_clk
, 1);
314 do_fixup_by_compat_u32(blob
, "fsl,elbc",
315 "bus-frequency", gd
->lbc_clk
, 1);
320 #ifdef CONFIG_SYS_NS16550
321 do_fixup_by_compat_u32(blob
, "ns16550",
322 "clock-frequency", CONFIG_SYS_NS16550_CLK
, 1);
326 do_fixup_by_compat_u32(blob
, "fsl,cpm2-scc-uart",
327 "current-speed", bd
->bi_baudrate
, 1);
329 do_fixup_by_compat_u32(blob
, "fsl,cpm2-brg",
330 "clock-frequency", bd
->bi_brgfreq
, 1);
333 fdt_fixup_memory(blob
, (u64
)bd
->bi_memstart
, (u64
)bd
->bi_memsize
);
336 ft_fixup_cpu(blob
, (u64
)bd
->bi_memstart
+ (u64
)bd
->bi_memsize
);
338 ft_fixup_num_cores(blob
);
340 ft_fixup_cache(blob
);
342 #if defined(CONFIG_FSL_ESDHC)
343 fdt_fixup_esdhc(blob
, bd
);