cpu/mpc85xx/mp.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/processor.h>
  25 #include <ioports.h>
  26 #include <lmb.h>
  27 #include <asm/io.h>
  28 #include "mp.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 u32 get_my_id()
  33 {
  34         return mfspr(SPRN_PIR);
  35 }
  36
  37 int cpu_reset(int nr)
  38 {
  39         volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
  40         out_be32(&pic->pir, 1 << nr);
  41         (void)in_be32(&pic->pir);
  42         out_be32(&pic->pir, 0x0);
  43
  44         return 0;
  45 }
  46
  47 int cpu_status(int nr)
  48 {
  49         u32 *table, id = get_my_id();
  50
  51         if (nr == id) {
  52                 table = (u32 *)get_spin_addr();
  53                 printf("table base @ 0x%p\n", table);
  54         } else {
  55                 table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
  56                 printf("Running on cpu %d\n", id);
  57                 printf("\n");
  58                 printf("table @ 0x%p\n", table);
  59                 printf("   addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
  60                 printf("   pir  - 0x%08x\n", table[BOOT_ENTRY_PIR]);
  61                 printf("   r3   - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
  62                 printf("   r6   - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]);
  63         }
  64
  65         return 0;
  66 }
  67
  68 static u8 boot_entry_map[4] = {
  69         0,
  70         BOOT_ENTRY_PIR,
  71         BOOT_ENTRY_R3_LOWER,
  72         BOOT_ENTRY_R6_LOWER,
  73 };
  74
  75 int cpu_release(int nr, int argc, char *argv[])
  76 {
  77         u32 i, val, *table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
  78         u64 boot_addr;
  79
  80         if (nr == get_my_id()) {
  81                 printf("Invalid to release the boot core.\n\n");
  82                 return 1;
  83         }
  84
  85         if (argc != 4) {
  86                 printf("Invalid number of arguments to release.\n\n");
  87                 return 1;
  88         }
  89
  90 #ifdef CFG_64BIT_STRTOUL
  91         boot_addr = simple_strtoull(argv[0], NULL, 16);
  92 #else
  93         boot_addr = simple_strtoul(argv[0], NULL, 16);
  94 #endif
  95
  96         /* handle pir, r3, r6 */
  97         for (i = 1; i < 4; i++) {
  98                 if (argv[i][0] != '-') {
  99                         u8 entry = boot_entry_map[i];
 100                         val = simple_strtoul(argv[i], NULL, 16);
 101                         table[entry] = val;
 102                 }
 103         }
 104
 105         table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
 106
 107         /* ensure all table updates complete before final address write */
 108         eieio();
 109
 110         table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
 111
 112         return 0;
 113 }
 114
 115 ulong get_spin_addr(void)
 116 {
 117         extern ulong __secondary_start_page;
 118         extern ulong __spin_table;
 119
 120         ulong addr =
 121                 (ulong)&__spin_table - (ulong)&__secondary_start_page;
 122         addr += 0xfffff000;
 123
 124         return addr;
 125 }
 126
 127 static void pq3_mp_up(unsigned long bootpg)
 128 {
 129         u32 up, cpu_up_mask, whoami;
 130         u32 *table = (u32 *)get_spin_addr();
 131         volatile u32 bpcr;
 132         volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
 133         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 134         volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
 135         u32 devdisr;
 136         int timeout = 10;
 137
 138         whoami = in_be32(&pic->whoami);
 139         out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
 140
 141         /* disable time base at the platform */
 142         devdisr = in_be32(&gur->devdisr);
 143         if (whoami)
 144                 devdisr |= MPC85xx_DEVDISR_TB0;
 145         else
 146                 devdisr |= MPC85xx_DEVDISR_TB1;
 147         out_be32(&gur->devdisr, devdisr);
 148
 149         /* release the hounds */
 150         up = ((1 << CONFIG_NUM_CPUS) - 1);
 151         bpcr = in_be32(&ecm->eebpcr);
 152         bpcr |= (up << 24);
 153         out_be32(&ecm->eebpcr, bpcr);
 154         asm("sync; isync; msync");
 155
 156         cpu_up_mask = 1 << whoami;
 157         /* wait for everyone */
 158         while (timeout) {
 159                 int i;
 160                 for (i = 0; i < CONFIG_NUM_CPUS; i++) {
 161                         if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
 162                                 cpu_up_mask |= (1 << i);
 163                 };
 164
 165                 if ((cpu_up_mask & up) == up)
 166                         break;
 167
 168                 udelay(100);
 169                 timeout--;
 170         }
 171
 172         if (timeout == 0)
 173                 printf("CPU up timeout. CPU up mask is %x should be %x\n",
 174                         cpu_up_mask, up);
 175
 176         /* enable time base at the platform */
 177         if (whoami)
 178                 devdisr |= MPC85xx_DEVDISR_TB1;
 179         else
 180                 devdisr |= MPC85xx_DEVDISR_TB0;
 181         out_be32(&gur->devdisr, devdisr);
 182         mtspr(SPRN_TBWU, 0);
 183         mtspr(SPRN_TBWL, 0);
 184
 185         devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
 186         out_be32(&gur->devdisr, devdisr);
 187 }
 188
 189 void cpu_mp_lmb_reserve(struct lmb *lmb)
 190 {
 191         u32 bootpg;
 192
 193         /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
 194         if ((u64)gd->ram_size > 0xfffff000)
 195                 bootpg = 0xfffff000;
 196         else
 197                 bootpg = gd->ram_size - 4096;
 198
 199         lmb_reserve(lmb, bootpg, 4096);
 200 }
 201
 202 void setup_mp(void)
 203 {
 204         extern ulong __secondary_start_page;
 205         ulong fixup = (ulong)&__secondary_start_page;
 206         u32 bootpg;
 207
 208         /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
 209         if ((u64)gd->ram_size > 0xfffff000)
 210                 bootpg = 0xfffff000;
 211         else
 212                 bootpg = gd->ram_size - 4096;
 213
 214         memcpy((void *)bootpg, (void *)fixup, 4096);
 215         flush_cache(bootpg, 4096);
 216
 217         pq3_mp_up(bootpg);
 218 }