cpu/mpc85xx/spd_sdram.c

   1 /*
   2  * Copyright 2004, 2007 Freescale Semiconductor.
   3  * (C) Copyright 2003 Motorola Inc.
   4  * Xianghua Xiao (X.Xiao@motorola.com)
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/processor.h>
  27 #include <i2c.h>
  28 #include <spd.h>
  29 #include <asm/mmu.h>
  30
  31
  32 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  33 extern void dma_init(void);
  34 extern uint dma_check(void);
  35 extern int dma_xfer(void *dest, uint count, void *src);
  36 #endif
  37
  38 #ifdef CONFIG_SPD_EEPROM
  39
  40 #ifndef CFG_READ_SPD
  41 #define CFG_READ_SPD    i2c_read
  42 #endif
  43
  44 static unsigned int setup_laws_and_tlbs(unsigned int memsize);
  45
  46
  47 /*
  48  * Convert picoseconds into clock cycles (rounding up if needed).
  49  */
  50
  51 int
  52 picos_to_clk(int picos)
  53 {
  54         int clks;
  55
  56         clks = picos / (2000000000 / (get_ddr_freq(0) / 1000));
  57         if (picos % (2000000000 / (get_ddr_freq(0) / 1000)) != 0) {
  58                 clks++;
  59         }
  60
  61         return clks;
  62 }
  63
  64
  65 /*
  66  * Calculate the Density of each Physical Rank.
  67  * Returned size is in bytes.
  68  *
  69  * Study these table from Byte 31 of JEDEC SPD Spec.
  70  *
  71  *              DDR I   DDR II
  72  *      Bit     Size    Size
  73  *      ---     -----   ------
  74  *      7 high  512MB   512MB
  75  *      6       256MB   256MB
  76  *      5       128MB   128MB
  77  *      4        64MB    16GB
  78  *      3        32MB     8GB
  79  *      2        16MB     4GB
  80  *      1         2GB     2GB
  81  *      0 low     1GB     1GB
  82  *
  83  * Reorder Table to be linear by stripping the bottom
  84  * 2 or 5 bits off and shifting them up to the top.
  85  */
  86
  87 unsigned int
  88 compute_banksize(unsigned int mem_type, unsigned char row_dens)
  89 {
  90         unsigned int bsize;
  91
  92         if (mem_type == SPD_MEMTYPE_DDR) {
  93                 /* Bottom 2 bits up to the top. */
  94                 bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
  95                 debug("DDR: DDR I rank density = 0x%08x\n", bsize);
  96         } else {
  97                 /* Bottom 5 bits up to the top. */
  98                 bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27;
  99                 debug("DDR: DDR II rank density = 0x%08x\n", bsize);
 100         }
 101         return bsize;
 102 }
 103
 104
 105 /*
 106  * Convert a two-nibble BCD value into a cycle time.
 107  * While the spec calls for nano-seconds, picos are returned.
 108  *
 109  * This implements the tables for bytes 9, 23 and 25 for both
 110  * DDR I and II.  No allowance for distinguishing the invalid
 111  * fields absent for DDR I yet present in DDR II is made.
 112  * (That is, cycle times of .25, .33, .66 and .75 ns are
 113  * allowed for both DDR II and I.)
 114  */
 115
 116 unsigned int
 117 convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
 118 {
 119         /*
 120          * Table look up the lower nibble, allow DDR I & II.
 121          */
 122         unsigned int tenths_ps[16] = {
 123                 0,
 124                 100,
 125                 200,
 126                 300,
 127                 400,
 128                 500,
 129                 600,
 130                 700,
 131                 800,
 132                 900,
 133                 250,
 134                 330,
 135                 660,
 136                 750,
 137                 0,      /* undefined */
 138                 0       /* undefined */
 139         };
 140
 141         unsigned int whole_ns = (spd_val & 0xF0) >> 4;
 142         unsigned int tenth_ns = spd_val & 0x0F;
 143         unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
 144
 145         return ps;
 146 }
 147
 148
 149 /*
 150  * Determine Refresh Rate.  Ignore self refresh bit on DDR I.
 151  * Table from SPD Spec, Byte 12, converted to picoseconds and
 152  * filled in with "default" normal values.
 153  */
 154 unsigned int determine_refresh_rate(unsigned int spd_refresh)
 155 {
 156         unsigned int refresh_time_ns[8] = {
 157                 15625000,       /* 0 Normal    1.00x */
 158                 3900000,        /* 1 Reduced    .25x */
 159                 7800000,        /* 2 Extended   .50x */
 160                 31300000,       /* 3 Extended  2.00x */
 161                 62500000,       /* 4 Extended  4.00x */
 162                 125000000,      /* 5 Extended  8.00x */
 163                 15625000,       /* 6 Normal    1.00x  filler */
 164                 15625000,       /* 7 Normal    1.00x  filler */
 165         };
 166
 167         return picos_to_clk(refresh_time_ns[spd_refresh & 0x7]);
 168 }
 169
 170
 171 long int
 172 spd_sdram(void)
 173 {
 174         volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
 175         spd_eeprom_t spd;
 176         unsigned int n_ranks;
 177         unsigned int rank_density;
 178         unsigned int odt_rd_cfg, odt_wr_cfg, ba_bits;
 179         unsigned int odt_cfg, mode_odt_enable;
 180         unsigned int refresh_clk;
 181 #ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
 182         unsigned char clk_adjust;
 183 #endif
 184         unsigned int dqs_cfg;
 185         unsigned char twr_clk, twtr_clk, twr_auto_clk;
 186         unsigned int tCKmin_ps, tCKmax_ps;
 187         unsigned int max_data_rate, effective_data_rate;
 188         unsigned int busfreq;
 189         unsigned sdram_cfg;
 190         unsigned int memsize = 0;
 191         unsigned char caslat, caslat_ctrl;
 192         unsigned int trfc, trfc_clk, trfc_low, trfc_high;
 193         unsigned int trcd_clk;
 194         unsigned int trtp_clk;
 195         unsigned char cke_min_clk;
 196         unsigned char add_lat;
 197         unsigned char wr_lat;
 198         unsigned char wr_data_delay;
 199         unsigned char four_act;
 200         unsigned char cpo;
 201         unsigned char burst_len;
 202         unsigned int mode_caslat;
 203         unsigned char sdram_type;
 204         unsigned char d_init;
 205         unsigned int bnds;
 206
 207         /*
 208          * Skip configuration if already configured.
 209          * memsize is determined from last configured chip select.
 210          */
 211         if (ddr->cs0_config & 0x80000000) {
 212                 debug(" cs0 already configured, bnds=%x\n",ddr->cs0_bnds);
 213                 bnds = 0xfff & ddr->cs0_bnds;
 214                 if (bnds < 0xff) { /* do not add if at top of 4G */
 215                         memsize = (bnds + 1) << 4;
 216                 }
 217         }
 218         if (ddr->cs1_config & 0x80000000) {
 219                 debug(" cs1 already configured, bnds=%x\n",ddr->cs1_bnds);
 220                 bnds = 0xfff & ddr->cs1_bnds;
 221                 if (bnds < 0xff) { /* do not add if at top of 4G */
 222                         memsize = (bnds + 1) << 4; /* assume ordered bnds */
 223                 }
 224         }
 225         if (ddr->cs2_config & 0x80000000) {
 226                 debug(" cs2 already configured, bnds=%x\n",ddr->cs2_bnds);
 227                 bnds = 0xfff & ddr->cs2_bnds;
 228                 if (bnds < 0xff) { /* do not add if at top of 4G */
 229                         memsize = (bnds + 1) << 4;
 230                 }
 231         }
 232         if (ddr->cs3_config & 0x80000000) {
 233                 debug(" cs3 already configured, bnds=%x\n",ddr->cs3_bnds);
 234                 bnds = 0xfff & ddr->cs3_bnds;
 235                 if (bnds < 0xff) { /* do not add if at top of 4G */
 236                         memsize = (bnds + 1) << 4;
 237                 }
 238         }
 239
 240         if (memsize) {
 241                 printf("       Reusing current %dMB configuration\n",memsize);
 242                 memsize = setup_laws_and_tlbs(memsize);
 243                 return memsize << 20;
 244         }
 245
 246         /*
 247          * Read SPD information.
 248          */
 249         CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) &spd, sizeof(spd));
 250
 251         /*
 252          * Check for supported memory module types.
 253          */
 254         if (spd.mem_type != SPD_MEMTYPE_DDR &&
 255             spd.mem_type != SPD_MEMTYPE_DDR2) {
 256                 printf("Unable to locate DDR I or DDR II module.\n"
 257                        "    Fundamental memory type is 0x%0x\n",
 258                        spd.mem_type);
 259                 return 0;
 260         }
 261
 262         /*
 263          * These test gloss over DDR I and II differences in interpretation
 264          * of bytes 3 and 4, but irrelevantly.  Multiple asymmetric banks
 265          * are not supported on DDR I; and not encoded on DDR II.
 266          *
 267          * Also note that the 8548 controller can support:
 268          *    12 <= nrow <= 16
 269          * and
 270          *     8 <= ncol <= 11 (still, for DDR)
 271          *     6 <= ncol <=  9 (for FCRAM)
 272          */
 273         if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
 274                 printf("DDR: Unsupported number of Row Addr lines: %d.\n",
 275                        spd.nrow_addr);
 276                 return 0;
 277         }
 278         if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
 279                 printf("DDR: Unsupported number of Column Addr lines: %d.\n",
 280                        spd.ncol_addr);
 281                 return 0;
 282         }
 283
 284         /*
 285          * Determine the number of physical banks controlled by
 286          * different Chip Select signals.  This is not quite the
 287          * same as the number of DIMM modules on the board.  Feh.
 288          */
 289         if (spd.mem_type == SPD_MEMTYPE_DDR) {
 290                 n_ranks = spd.nrows;
 291         } else {
 292                 n_ranks = (spd.nrows & 0x7) + 1;
 293         }
 294
 295         debug("DDR: number of ranks = %d\n", n_ranks);
 296
 297         if (n_ranks > 2) {
 298                 printf("DDR: Only 2 chip selects are supported: %d\n",
 299                        n_ranks);
 300                 return 0;
 301         }
 302
 303 #ifdef CONFIG_MPC8548
 304         /*
 305          * Adjust DDR II IO voltage biasing.
 306          * Only 8548 rev 1 needs the fix
 307          */
 308         if ((SVR_VER(get_svr()) == SVR_8548_E) &&
 309                         (SVR_MJREV(get_svr()) == 1) &&
 310                         (spd.mem_type == SPD_MEMTYPE_DDR2)) {
 311                 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 312                 gur->ddrioovcr = (0x80000000    /* Enable */
 313                                   | 0x10000000);/* VSEL to 1.8V */
 314         }
 315 #endif
 316
 317         /*
 318          * Determine the size of each Rank in bytes.
 319          */
 320         rank_density = compute_banksize(spd.mem_type, spd.row_dens);
 321
 322
 323         /*
 324          * Eg: Bounds: 0x0000_0000 to 0x0f000_0000      first 256 Meg
 325          */
 326         ddr->cs0_bnds = (rank_density >> 24) - 1;
 327
 328         /*
 329          * ODT configuration recommendation from DDR Controller Chapter.
 330          */
 331         odt_rd_cfg = 0;                 /* Never assert ODT */
 332         odt_wr_cfg = 0;                 /* Never assert ODT */
 333         if (spd.mem_type == SPD_MEMTYPE_DDR2) {
 334                 odt_wr_cfg = 1;         /* Assert ODT on writes to CS0 */
 335 #if 0
 336                 /* FIXME: How to determine the number of dimm modules? */
 337                 if (n_dimm_modules == 2) {
 338                         odt_rd_cfg = 1; /* Assert ODT on reads to CS0 */
 339                 }
 340 #endif
 341         }
 342
 343         ba_bits = 0;
 344         if (spd.nbanks == 0x8)
 345                 ba_bits = 1;
 346
 347         ddr->cs0_config = ( 1 << 31
 348                             | (odt_rd_cfg << 20)
 349                             | (odt_wr_cfg << 16)
 350                             | (ba_bits << 14)
 351                             | (spd.nrow_addr - 12) << 8
 352                             | (spd.ncol_addr - 8) );
 353         debug("\n");
 354         debug("DDR: cs0_bnds   = 0x%08x\n", ddr->cs0_bnds);
 355         debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
 356
 357         if (n_ranks == 2) {
 358                 /*
 359                  * Eg: Bounds: 0x0f00_0000 to 0x1e0000_0000, second 256 Meg
 360                  */
 361                 ddr->cs1_bnds = ( (rank_density >> 8)
 362                                   | ((rank_density >> (24 - 1)) - 1) );
 363                 ddr->cs1_config = ( 1<<31
 364                                     | (odt_rd_cfg << 20)
 365                                     | (odt_wr_cfg << 16)
 366                                     | (spd.nrow_addr - 12) << 8
 367                                     | (spd.ncol_addr - 8) );
 368                 debug("DDR: cs1_bnds   = 0x%08x\n", ddr->cs1_bnds);
 369                 debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config);
 370         }
 371
 372
 373         /*
 374          * Find the largest CAS by locating the highest 1 bit
 375          * in the spd.cas_lat field.  Translate it to a DDR
 376          * controller field value:
 377          *
 378          *      CAS Lat DDR I   DDR II  Ctrl
 379          *      Clocks  SPD Bit SPD Bit Value
 380          *      ------- ------- ------- -----
 381          *      1.0     0               0001
 382          *      1.5     1               0010
 383          *      2.0     2       2       0011
 384          *      2.5     3               0100
 385          *      3.0     4       3       0101
 386          *      3.5     5               0110
 387          *      4.0             4       0111
 388          *      4.5                     1000
 389          *      5.0             5       1001
 390          */
 391         caslat = __ilog2(spd.cas_lat);
 392         if ((spd.mem_type == SPD_MEMTYPE_DDR)
 393             && (caslat > 5)) {
 394                 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
 395                 return 0;
 396
 397         } else if (spd.mem_type == SPD_MEMTYPE_DDR2
 398                    && (caslat < 2 || caslat > 5)) {
 399                 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
 400                        spd.cas_lat);
 401                 return 0;
 402         }
 403         debug("DDR: caslat SPD bit is %d\n", caslat);
 404
 405         /*
 406          * Calculate the Maximum Data Rate based on the Minimum Cycle time.
 407          * The SPD clk_cycle field (tCKmin) is measured in tenths of
 408          * nanoseconds and represented as BCD.
 409          */
 410         tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle);
 411         debug("DDR: tCKmin = %d ps\n", tCKmin_ps);
 412
 413         /*
 414          * Double-data rate, scaled 1000 to picoseconds, and back down to MHz.
 415          */
 416         max_data_rate = 2 * 1000 * 1000 / tCKmin_ps;
 417         debug("DDR: Module max data rate = %d Mhz\n", max_data_rate);
 418
 419
 420         /*
 421          * Adjust the CAS Latency to allow for bus speeds that
 422          * are slower than the DDR module.
 423          */
 424         busfreq = get_ddr_freq(0) / 1000000;    /* MHz */
 425
 426         effective_data_rate = max_data_rate;
 427         if (busfreq < 90) {
 428                 /* DDR rate out-of-range */
 429                 puts("DDR: platform frequency is not fit for DDR rate\n");
 430                 return 0;
 431
 432         } else if (90 <= busfreq && busfreq < 230 && max_data_rate >= 230) {
 433                 /*
 434                  * busfreq 90~230 range, treated as DDR 200.
 435                  */
 436                 effective_data_rate = 200;
 437                 if (spd.clk_cycle3 == 0xa0)     /* 10 ns */
 438                         caslat -= 2;
 439                 else if (spd.clk_cycle2 == 0xa0)
 440                         caslat--;
 441
 442         } else if (230 <= busfreq && busfreq < 280 && max_data_rate >= 280) {
 443                 /*
 444                  * busfreq 230~280 range, treated as DDR 266.
 445                  */
 446                 effective_data_rate = 266;
 447                 if (spd.clk_cycle3 == 0x75)     /* 7.5 ns */
 448                         caslat -= 2;
 449                 else if (spd.clk_cycle2 == 0x75)
 450                         caslat--;
 451
 452         } else if (280 <= busfreq && busfreq < 350 && max_data_rate >= 350) {
 453                 /*
 454                  * busfreq 280~350 range, treated as DDR 333.
 455                  */
 456                 effective_data_rate = 333;
 457                 if (spd.clk_cycle3 == 0x60)     /* 6.0 ns */
 458                         caslat -= 2;
 459                 else if (spd.clk_cycle2 == 0x60)
 460                         caslat--;
 461
 462         } else if (350 <= busfreq && busfreq < 460 && max_data_rate >= 460) {
 463                 /*
 464                  * busfreq 350~460 range, treated as DDR 400.
 465                  */
 466                 effective_data_rate = 400;
 467                 if (spd.clk_cycle3 == 0x50)     /* 5.0 ns */
 468                         caslat -= 2;
 469                 else if (spd.clk_cycle2 == 0x50)
 470                         caslat--;
 471
 472         } else if (460 <= busfreq && busfreq < 560 && max_data_rate >= 560) {
 473                 /*
 474                  * busfreq 460~560 range, treated as DDR 533.
 475                  */
 476                 effective_data_rate = 533;
 477                 if (spd.clk_cycle3 == 0x3D)     /* 3.75 ns */
 478                         caslat -= 2;
 479                 else if (spd.clk_cycle2 == 0x3D)
 480                         caslat--;
 481
 482         } else if (560 <= busfreq && busfreq < 700 && max_data_rate >= 700) {
 483                 /*
 484                  * busfreq 560~700 range, treated as DDR 667.
 485                  */
 486                 effective_data_rate = 667;
 487                 if (spd.clk_cycle3 == 0x30)     /* 3.0 ns */
 488                         caslat -= 2;
 489                 else if (spd.clk_cycle2 == 0x30)
 490                         caslat--;
 491
 492         } else if (700 <= busfreq) {
 493                 /*
 494                  * DDR rate out-of-range
 495                  */
 496                 printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
 497                      busfreq, max_data_rate);
 498                 return 0;
 499         }
 500
 501
 502         /*
 503          * Convert caslat clocks to DDR controller value.
 504          * Force caslat_ctrl to be DDR Controller field-sized.
 505          */
 506         if (spd.mem_type == SPD_MEMTYPE_DDR) {
 507                 caslat_ctrl = (caslat + 1) & 0x07;
 508         } else {
 509                 caslat_ctrl =  (2 * caslat - 1) & 0x0f;
 510         }
 511
 512         debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
 513         debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
 514               caslat, caslat_ctrl);
 515
 516         /*
 517          * Timing Config 0.
 518          * Avoid writing for DDR I.  The new PQ38 DDR controller
 519          * dreams up non-zero default values to be backwards compatible.
 520          */
 521         if (spd.mem_type == SPD_MEMTYPE_DDR2) {
 522                 unsigned char taxpd_clk = 8;            /* By the book. */
 523                 unsigned char tmrd_clk = 2;             /* By the book. */
 524                 unsigned char act_pd_exit = 2;          /* Empirical? */
 525                 unsigned char pre_pd_exit = 6;          /* Empirical? */
 526
 527                 ddr->timing_cfg_0 = (0
 528                         | ((act_pd_exit & 0x7) << 20)   /* ACT_PD_EXIT */
 529                         | ((pre_pd_exit & 0x7) << 16)   /* PRE_PD_EXIT */
 530                         | ((taxpd_clk & 0xf) << 8)      /* ODT_PD_EXIT */
 531                         | ((tmrd_clk & 0xf) << 0)       /* MRS_CYC */
 532                         );
 533 #if 0
 534                 ddr->timing_cfg_0 |= 0xaa000000;        /* extra cycles */
 535 #endif
 536                 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 537
 538         } else {
 539 #if 0
 540                 /*
 541                  * Force extra cycles with 0xaa bits.
 542                  * Incidentally supply the dreamt-up backwards compat value!
 543                  */
 544                 ddr->timing_cfg_0 = 0x00110105; /* backwards compat value */
 545                 ddr->timing_cfg_0 |= 0xaa000000;        /* extra cycles */
 546                 debug("DDR: HACK timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 547 #endif
 548         }
 549
 550
 551         /*
 552          * Some Timing Config 1 values now.
 553          * Sneak Extended Refresh Recovery in here too.
 554          */
 555
 556         /*
 557          * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
 558          * use conservative value.
 559          * For DDR II, they are bytes 36 and 37, in quarter nanos.
 560          */
 561
 562         if (spd.mem_type == SPD_MEMTYPE_DDR) {
 563                 twr_clk = 3;    /* Clocks */
 564                 twtr_clk = 1;   /* Clocks */
 565         } else {
 566                 twr_clk = picos_to_clk(spd.twr * 250);
 567                 twtr_clk = picos_to_clk(spd.twtr * 250);
 568         }
 569
 570         /*
 571          * Calculate Trfc, in picos.
 572          * DDR I:  Byte 42 straight up in ns.
 573          * DDR II: Byte 40 and 42 swizzled some, in ns.
 574          */
 575         if (spd.mem_type == SPD_MEMTYPE_DDR) {
 576                 trfc = spd.trfc * 1000;         /* up to ps */
 577         } else {
 578                 unsigned int byte40_table_ps[8] = {
 579                         0,
 580                         250,
 581                         330,
 582                         500,
 583                         660,
 584                         750,
 585                         0,
 586                         0
 587                 };
 588
 589                 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
 590                         + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
 591         }
 592         trfc_clk = picos_to_clk(trfc);
 593
 594         /*
 595          * Trcd, Byte 29, from quarter nanos to ps and clocks.
 596          */
 597         trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
 598
 599         /*
 600          * Convert trfc_clk to DDR controller fields.  DDR I should
 601          * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
 602          * 8548 controller has an extended REFREC field of three bits.
 603          * The controller automatically adds 8 clocks to this value,
 604          * so preadjust it down 8 first before splitting it up.
 605          */
 606         trfc_low = (trfc_clk - 8) & 0xf;
 607         trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
 608
 609         /*
 610          * Sneak in some Extended Refresh Recovery.
 611          */
 612         ddr->ext_refrec = (trfc_high << 16);
 613         debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
 614
 615         ddr->timing_cfg_1 =
 616             (0
 617              | ((picos_to_clk(spd.trp * 250) & 0x07) << 28)     /* PRETOACT */
 618              | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24)  /* ACTTOPRE */
 619              | (trcd_clk << 20)                                 /* ACTTORW */
 620              | (caslat_ctrl << 16)                              /* CASLAT */
 621              | (trfc_low << 12)                                 /* REFEC */
 622              | ((twr_clk & 0x07) << 8)                          /* WRRREC */
 623              | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4)     /* ACTTOACT */
 624              | ((twtr_clk & 0x07) << 0)                         /* WRTORD */
 625              );
 626
 627         debug("DDR: timing_cfg_1  = 0x%08x\n", ddr->timing_cfg_1);
 628
 629
 630         /*
 631          * Timing_Config_2
 632          * Was: 0x00000800;
 633          */
 634
 635         /*
 636          * Additive Latency
 637          * For DDR I, 0.
 638          * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
 639          * which comes from Trcd, and also note that:
 640          *      add_lat + caslat must be >= 4
 641          */
 642         add_lat = 0;
 643         if (spd.mem_type == SPD_MEMTYPE_DDR2
 644             && (odt_wr_cfg || odt_rd_cfg)
 645             && (caslat < 4)) {
 646                 add_lat = 4 - caslat;
 647                 if (add_lat > trcd_clk) {
 648                         add_lat = trcd_clk - 1;
 649                 }
 650         }
 651
 652         /*
 653          * Write Data Delay
 654          * Historically 0x2 == 4/8 clock delay.
 655          * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
 656          */
 657         wr_data_delay = 3;
 658
 659         /*
 660          * Write Latency
 661          * Read to Precharge
 662          * Minimum CKE Pulse Width.
 663          * Four Activate Window
 664          */
 665         if (spd.mem_type == SPD_MEMTYPE_DDR) {
 666                 /*
 667                  * This is a lie.  It should really be 1, but if it is
 668                  * set to 1, bits overlap into the old controller's
 669                  * otherwise unused ACSM field.  If we leave it 0, then
 670                  * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 671                  */
 672                 wr_lat = 0;
 673
 674                 trtp_clk = 2;           /* By the book. */
 675                 cke_min_clk = 1;        /* By the book. */
 676                 four_act = 1;           /* By the book. */
 677
 678         } else {
 679                 wr_lat = caslat - 1;
 680
 681                 /* Convert SPD value from quarter nanos to picos. */
 682                 trtp_clk = picos_to_clk(spd.trtp * 250);
 683
 684                 cke_min_clk = 3;        /* By the book. */
 685                 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
 686         }
 687
 688         /*
 689          * Empirically set ~MCAS-to-preamble override for DDR 2.
 690          * Your milage will vary.
 691          */
 692         cpo = 0;
 693         if (spd.mem_type == SPD_MEMTYPE_DDR2) {
 694                 if (effective_data_rate <= 333) {
 695                         cpo = 0x7;              /* READ_LAT + 5/4 */
 696                 } else {
 697                         cpo = 0x9;              /* READ_LAT + 7/4 */
 698                 }
 699         }
 700
 701         ddr->timing_cfg_2 = (0
 702                 | ((add_lat & 0x7) << 28)               /* ADD_LAT */
 703                 | ((cpo & 0x1f) << 23)                  /* CPO */
 704                 | ((wr_lat & 0x7) << 19)                /* WR_LAT */
 705                 | ((trtp_clk & 0x7) << 13)              /* RD_TO_PRE */
 706                 | ((wr_data_delay & 0x7) << 10)         /* WR_DATA_DELAY */
 707                 | ((cke_min_clk & 0x7) << 6)            /* CKE_PLS */
 708                 | ((four_act & 0x1f) << 0)              /* FOUR_ACT */
 709                 );
 710
 711         debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 712
 713
 714         /*
 715          * Determine the Mode Register Set.
 716          *
 717          * This is nominally part specific, but it appears to be
 718          * consistent for all DDR I devices, and for all DDR II devices.
 719          *
 720          *     caslat must be programmed
 721          *     burst length is always 4
 722          *     burst type is sequential
 723          *
 724          * For DDR I:
 725          *     operating mode is "normal"
 726          *
 727          * For DDR II:
 728          *     other stuff
 729          */
 730
 731         mode_caslat = 0;
 732
 733         /*
 734          * Table lookup from DDR I or II Device Operation Specs.
 735          */
 736         if (spd.mem_type == SPD_MEMTYPE_DDR) {
 737                 if (1 <= caslat && caslat <= 4) {
 738                         unsigned char mode_caslat_table[4] = {
 739                                 0x5,    /* 1.5 clocks */
 740                                 0x2,    /* 2.0 clocks */
 741                                 0x6,    /* 2.5 clocks */
 742                                 0x3     /* 3.0 clocks */
 743                         };
 744                         mode_caslat = mode_caslat_table[caslat - 1];
 745                 } else {
 746                         puts("DDR I: Only CAS Latencies of 1.5, 2.0, "
 747                              "2.5 and 3.0 clocks are supported.\n");
 748                         return 0;
 749                 }
 750
 751         } else {
 752                 if (2 <= caslat && caslat <= 5) {
 753                         mode_caslat = caslat;
 754                 } else {
 755                         puts("DDR II: Only CAS Latencies of 2.0, 3.0, "
 756                              "4.0 and 5.0 clocks are supported.\n");
 757                         return 0;
 758                 }
 759         }
 760
 761         /*
 762          * Encoded Burst Lenght of 4.
 763          */
 764         burst_len = 2;                  /* Fiat. */
 765
 766         if (spd.mem_type == SPD_MEMTYPE_DDR) {
 767                 twr_auto_clk = 0;       /* Historical */
 768         } else {
 769                 /*
 770                  * Determine tCK max in picos.  Grab tWR and convert to picos.
 771                  * Auto-precharge write recovery is:
 772                  *      WR = roundup(tWR_ns/tCKmax_ns).
 773                  *
 774                  * Ponder: Is twr_auto_clk different than twr_clk?
 775                  */
 776                 tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax);
 777                 twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps;
 778         }
 779
 780
 781         /*
 782          * Mode Reg in bits 16 ~ 31,
 783          * Extended Mode Reg 1 in bits 0 ~ 15.
 784          */
 785         mode_odt_enable = 0x0;                  /* Default disabled */
 786         if (odt_wr_cfg || odt_rd_cfg) {
 787                 /*
 788                  * Bits 6 and 2 in Extended MRS(1)
 789                  * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
 790                  * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
 791                  */
 792                 mode_odt_enable = 0x40;         /* 150 Ohm */
 793         }
 794
 795         ddr->sdram_mode =
 796                 (0
 797                  | (add_lat << (16 + 3))        /* Additive Latency in EMRS1 */
 798                  | (mode_odt_enable << 16)      /* ODT Enable in EMRS1 */
 799                  | (twr_auto_clk << 9)          /* Write Recovery Autopre */
 800                  | (mode_caslat << 4)           /* caslat */
 801                  | (burst_len << 0)             /* Burst length */
 802                  );
 803
 804         debug("DDR: sdram_mode   = 0x%08x\n", ddr->sdram_mode);
 805
 806
 807         /*
 808          * Clear EMRS2 and EMRS3.
 809          */
 810         ddr->sdram_mode_2 = 0;
 811         debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2);
 812
 813         /*
 814          * Determine Refresh Rate.
 815          */
 816         refresh_clk = determine_refresh_rate(spd.refresh & 0x7);
 817
 818         /*
 819          * Set BSTOPRE to 0x100 for page mode
 820          * If auto-charge is used, set BSTOPRE = 0
 821          */
 822         ddr->sdram_interval =
 823             (0
 824              | (refresh_clk & 0x3fff) << 16
 825              | 0x100
 826              );
 827         debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
 828
 829         /*
 830          * Is this an ECC DDR chip?
 831          * But don't mess with it if the DDR controller will init mem.
 832          */
 833 #ifdef CONFIG_DDR_ECC
 834         if (spd.config == 0x02) {
 835 #ifndef CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 836                 ddr->err_disable = 0x0000000d;
 837 #endif
 838                 ddr->err_sbe = 0x00ff0000;
 839         }
 840
 841         debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
 842         debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
 843 #endif /* CONFIG_DDR_ECC */
 844
 845         asm("sync;isync;msync");
 846         udelay(500);
 847
 848         /*
 849          * SDRAM Cfg 2
 850          */
 851
 852         /*
 853          * When ODT is enabled, Chap 9 suggests asserting ODT to
 854          * internal IOs only during reads.
 855          */
 856         odt_cfg = 0;
 857         if (odt_rd_cfg | odt_wr_cfg) {
 858                 odt_cfg = 0x2;          /* ODT to IOs during reads */
 859         }
 860
 861         /*
 862          * Try to use differential DQS with DDR II.
 863          */
 864         if (spd.mem_type == SPD_MEMTYPE_DDR) {
 865                 dqs_cfg = 0;            /* No Differential DQS for DDR I */
 866         } else {
 867                 dqs_cfg = 0x1;          /* Differential DQS for DDR II */
 868         }
 869
 870 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 871         /*
 872          * Use the DDR controller to auto initialize memory.
 873          */
 874         d_init = 1;
 875         ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE;
 876         debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init);
 877 #else
 878         /*
 879          * Memory will be initialized via DMA, or not at all.
 880          */
 881         d_init = 0;
 882 #endif
 883
 884         ddr->sdram_cfg_2 = (0
 885                             | (dqs_cfg << 26)   /* Differential DQS */
 886                             | (odt_cfg << 21)   /* ODT */
 887                             | (d_init << 4)     /* D_INIT auto init DDR */
 888                             );
 889
 890         debug("DDR: sdram_cfg_2  = 0x%08x\n", ddr->sdram_cfg_2);
 891
 892
 893 #ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
 894         /*
 895          * Setup the clock control.
 896          * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
 897          * SDRAM_CLK_CNTL[5-7] = Clock Adjust
 898          *      0110    3/4 cycle late
 899          *      0111    7/8 cycle late
 900          */
 901         if (spd.mem_type == SPD_MEMTYPE_DDR)
 902                 clk_adjust = 0x6;
 903         else
 904 #ifdef CONFIG_MPC8568
 905                 /* Empirally setting clk_adjust */
 906                 clk_adjust = 0x6;
 907 #else
 908                 clk_adjust = 0x7;
 909 #endif
 910
 911         ddr->sdram_clk_cntl = (0
 912                                | 0x80000000
 913                                | (clk_adjust << 23)
 914                                );
 915         debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
 916 #endif
 917
 918         /*
 919          * Figure out the settings for the sdram_cfg register.
 920          * Build up the entire register in 'sdram_cfg' before writing
 921          * since the write into the register will actually enable the
 922          * memory controller; all settings must be done before enabling.
 923          *
 924          * sdram_cfg[0]   = 1 (ddr sdram logic enable)
 925          * sdram_cfg[1]   = 1 (self-refresh-enable)
 926          * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
 927          *                      010 DDR 1 SDRAM
 928          *                      011 DDR 2 SDRAM
 929          */
 930         sdram_type = (spd.mem_type == SPD_MEMTYPE_DDR) ? 2 : 3;
 931         sdram_cfg = (0
 932                      | (1 << 31)                        /* Enable */
 933                      | (1 << 30)                        /* Self refresh */
 934                      | (sdram_type << 24)               /* SDRAM type */
 935                      );
 936
 937         /*
 938          * sdram_cfg[3] = RD_EN - registered DIMM enable
 939          *   A value of 0x26 indicates micron registered DIMMS (micron.com)
 940          */
 941         if (spd.mem_type == SPD_MEMTYPE_DDR && spd.mod_attr == 0x26) {
 942                 sdram_cfg |= 0x10000000;                /* RD_EN */
 943         }
 944
 945 #if defined(CONFIG_DDR_ECC)
 946         /*
 947          * If the user wanted ECC (enabled via sdram_cfg[2])
 948          */
 949         if (spd.config == 0x02) {
 950                 sdram_cfg |= 0x20000000;                /* ECC_EN */
 951         }
 952 #endif
 953
 954         /*
 955          * REV1 uses 1T timing.
 956          * REV2 may use 1T or 2T as configured by the user.
 957          */
 958         {
 959                 uint pvr = get_pvr();
 960
 961                 if (pvr != PVR_85xx_REV1) {
 962 #if defined(CONFIG_DDR_2T_TIMING)
 963                         /*
 964                          * Enable 2T timing by setting sdram_cfg[16].
 965                          */
 966                         sdram_cfg |= 0x8000;            /* 2T_EN */
 967 #endif
 968                 }
 969         }
 970
 971         /*
 972          * 200 painful micro-seconds must elapse between
 973          * the DDR clock setup and the DDR config enable.
 974          */
 975         udelay(200);
 976
 977         /*
 978          * Go!
 979          */
 980         ddr->sdram_cfg = sdram_cfg;
 981
 982         asm("sync;isync;msync");
 983         udelay(500);
 984
 985         debug("DDR: sdram_cfg   = 0x%08x\n", ddr->sdram_cfg);
 986
 987
 988 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 989         /*
 990          * Poll until memory is initialized.
 991          * 512 Meg at 400 might hit this 200 times or so.
 992          */
 993         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
 994                 udelay(1000);
 995         }
 996 #endif
 997
 998
 999         /*
1000          * Figure out memory size in Megabytes.
1001          */
1002         memsize = n_ranks * rank_density / 0x100000;
1003
1004         /*
1005          * Establish Local Access Window and TLB mappings for DDR memory.
1006          */
1007         memsize = setup_laws_and_tlbs(memsize);
1008         if (memsize == 0) {
1009                 return 0;
1010         }
1011
1012         return memsize * 1024 * 1024;
1013 }
1014
1015
1016 /*
1017  * Setup Local Access Window and TLB1 mappings for the requested
1018  * amount of memory.  Returns the amount of memory actually mapped
1019  * (usually the original request size), or 0 on error.
1020  */
1021
1022 static unsigned int
1023 setup_laws_and_tlbs(unsigned int memsize)
1024 {
1025         volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
1026         unsigned int tlb_size;
1027         unsigned int law_size;
1028         unsigned int ram_tlb_index;
1029         unsigned int ram_tlb_address;
1030
1031         /*
1032          * Determine size of each TLB1 entry.
1033          */
1034         switch (memsize) {
1035         case 16:
1036         case 32:
1037                 tlb_size = BOOKE_PAGESZ_16M;
1038                 break;
1039         case 64:
1040         case 128:
1041                 tlb_size = BOOKE_PAGESZ_64M;
1042                 break;
1043         case 256:
1044         case 512:
1045                 tlb_size = BOOKE_PAGESZ_256M;
1046                 break;
1047         case 1024:
1048         case 2048:
1049                 if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
1050                         tlb_size = BOOKE_PAGESZ_1G;
1051                 else
1052                         tlb_size = BOOKE_PAGESZ_256M;
1053                 break;
1054         default:
1055                 puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n");
1056
1057                 /*
1058                  * The memory was not able to be mapped.
1059                  * Default to a small size.
1060                  */
1061                 tlb_size = BOOKE_PAGESZ_64M;
1062                 memsize=64;
1063                 break;
1064         }
1065
1066         /*
1067          * Configure DDR TLB1 entries.
1068          * Starting at TLB1 8, use no more than 8 TLB1 entries.
1069          */
1070         ram_tlb_index = 8;
1071         ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
1072         while (ram_tlb_address < (memsize * 1024 * 1024)
1073               && ram_tlb_index < 16) {
1074                 mtspr(MAS0, FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
1075                 mtspr(MAS1, FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
1076                 mtspr(MAS2, FSL_BOOKE_MAS2(ram_tlb_address, 0));
1077                 mtspr(MAS3, FSL_BOOKE_MAS3(ram_tlb_address, 0,
1078                         (MAS3_SX|MAS3_SW|MAS3_SR)));
1079                 asm volatile("isync;msync;tlbwe;isync");
1080
1081                 debug("DDR: MAS0=0x%08x\n", FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
1082                 debug("DDR: MAS1=0x%08x\n", FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
1083                 debug("DDR: MAS2=0x%08x\n", FSL_BOOKE_MAS2(ram_tlb_address, 0));
1084                 debug("DDR: MAS3=0x%08x\n",
1085                         FSL_BOOKE_MAS3(ram_tlb_address, 0,
1086                                       (MAS3_SX|MAS3_SW|MAS3_SR)));
1087
1088                 ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
1089                 ram_tlb_index++;
1090         }
1091
1092
1093         /*
1094          * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.  Fnord.
1095          */
1096         law_size = 19 + __ilog2(memsize);
1097
1098         /*
1099          * Set up LAWBAR for all of DDR.
1100          */
1101         ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1102         ecm->lawar1 = (LAWAR_EN
1103                        | LAWAR_TRGT_IF_DDR
1104                        | (LAWAR_SIZE & law_size));
1105         debug("DDR: LAWBAR1=0x%08x\n", ecm->lawbar1);
1106         debug("DDR: LARAR1=0x%08x\n", ecm->lawar1);
1107
1108         /*
1109          * Confirm that the requested amount of memory was mapped.
1110          */
1111         return memsize;
1112 }
1113
1114 #endif /* CONFIG_SPD_EEPROM */
1115
1116
1117 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
1118
1119 /*
1120  * Initialize all of memory for ECC, then enable errors.
1121  */
1122
1123 void
1124 ddr_enable_ecc(unsigned int dram_size)
1125 {
1126         uint *p = 0;
1127         uint i = 0;
1128         volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
1129
1130         dma_init();
1131
1132         for (*p = 0; p < (uint *)(8 * 1024); p++) {
1133                 if (((unsigned int)p & 0x1f) == 0) {
1134                         ppcDcbz((unsigned long) p);
1135                 }
1136                 *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
1137                 if (((unsigned int)p & 0x1c) == 0x1c) {
1138                         ppcDcbf((unsigned long) p);
1139                 }
1140         }
1141
1142         dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
1143         dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
1144         dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
1145         dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
1146         dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
1147         dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
1148         dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
1149         dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
1150         dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
1151         dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
1152
1153         for (i = 1; i < dram_size / 0x800000; i++) {
1154                 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
1155         }
1156
1157         /*
1158          * Enable errors for ECC.
1159          */
1160         debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
1161         ddr->err_disable = 0x00000000;
1162         asm("sync;isync;msync");
1163         debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
1164 }
1165
1166 #endif  /* CONFIG_DDR_ECC  && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */