cpu/mpc85xx/speed.c

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * (C) Copyright 2003 Motorola Inc.
   4  * Xianghua Xiao, (X.Xiao@motorola.com)
   5  *
   6  * (C) Copyright 2000
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <ppc_asm.tmpl>
  30 #include <asm/processor.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 /* --------------------------------------------------------------- */
  35
  36 void get_sys_info (sys_info_t * sysInfo)
  37 {
  38         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  39         uint plat_ratio,e500_ratio,half_freqSystemBus;
  40
  41         plat_ratio = (gur->porpllsr) & 0x0000003e;
  42         plat_ratio >>= 1;
  43         sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
  44         e500_ratio = (gur->porpllsr) & 0x003f0000;
  45         e500_ratio >>= 16;
  46
  47         /* Divide before multiply to avoid integer
  48          * overflow for processor speeds above 2GHz */
  49         half_freqSystemBus = sysInfo->freqSystemBus/2;
  50         sysInfo->freqProcessor = e500_ratio*half_freqSystemBus;
  51
  52         /* Note: freqDDRBus is the MCLK frequency, not the data rate. */
  53         sysInfo->freqDDRBus = sysInfo->freqSystemBus;
  54
  55 #ifdef CONFIG_DDR_CLK_FREQ
  56         {
  57                 u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
  58                 if (ddr_ratio != 0x7)
  59                         sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
  60         }
  61 #endif
  62 }
  63
  64
  65 int get_clocks (void)
  66 {
  67         sys_info_t sys_info;
  68 #ifdef CONFIG_MPC8544
  69         volatile ccsr_gur_t *gur = (void *) CFG_MPC85xx_GUTS_ADDR;
  70 #endif
  71 #if defined(CONFIG_CPM2)
  72         volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
  73         uint sccr, dfbrg;
  74
  75         /* set VCO = 4 * BRG */
  76         cpm->im_cpm_intctl.sccr &= 0xfffffffc;
  77         sccr = cpm->im_cpm_intctl.sccr;
  78         dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
  79 #endif
  80         get_sys_info (&sys_info);
  81         gd->cpu_clk = sys_info.freqProcessor;
  82         gd->bus_clk = sys_info.freqSystemBus;
  83         gd->mem_clk = sys_info.freqDDRBus;
  84
  85         /*
  86          * The base clock for I2C depends on the actual SOC.  Unfortunately,
  87          * there is no pattern that can be used to determine the frequency, so
  88          * the only choice is to look up the actual SOC number and use the value
  89          * for that SOC. This information is taken from application note
  90          * AN2919.
  91          */
  92 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
  93         defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
  94         gd->i2c1_clk = sys_info.freqSystemBus;
  95 #elif defined(CONFIG_MPC8544)
  96         /*
  97          * On the 8544, the I2C clock is the same as the SEC clock.  This can be
  98          * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
  99          * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
 100          * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
 101          * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
 102          */
 103         if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
 104                 gd->i2c1_clk = sys_info.freqSystemBus / 3;
 105         else
 106                 gd->i2c1_clk = sys_info.freqSystemBus / 2;
 107 #else
 108         /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
 109         gd->i2c1_clk = sys_info.freqSystemBus / 2;
 110 #endif
 111         gd->i2c2_clk = gd->i2c1_clk;
 112
 113 #if defined(CONFIG_CPM2)
 114         gd->vco_out = 2*sys_info.freqSystemBus;
 115         gd->cpm_clk = gd->vco_out / 2;
 116         gd->scc_clk = gd->vco_out / 4;
 117         gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
 118 #endif
 119
 120         if(gd->cpu_clk != 0) return (0);
 121         else return (1);
 122 }
 123
 124
 125 /********************************************
 126  * get_bus_freq
 127  * return system bus freq in Hz
 128  *********************************************/
 129 ulong get_bus_freq (ulong dummy)
 130 {
 131         return gd->bus_clk;
 132 }
 133
 134 /********************************************
 135  * get_ddr_freq
 136  * return ddr bus freq in Hz
 137  *********************************************/
 138 ulong get_ddr_freq (ulong dummy)
 139 {
 140         return gd->mem_clk;
 141 }