2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <ppc_asm.tmpl>
30 #include <asm/processor.h>
32 DECLARE_GLOBAL_DATA_PTR
;
34 /* --------------------------------------------------------------- */
36 void get_sys_info (sys_info_t
* sysInfo
)
38 volatile ccsr_gur_t
*gur
= (void *)(CFG_MPC85xx_GUTS_ADDR
);
39 uint plat_ratio
,e500_ratio
,half_freqSystemBus
;
41 plat_ratio
= (gur
->porpllsr
) & 0x0000003e;
43 sysInfo
->freqSystemBus
= plat_ratio
* CONFIG_SYS_CLK_FREQ
;
44 e500_ratio
= (gur
->porpllsr
) & 0x003f0000;
47 /* Divide before multiply to avoid integer
48 * overflow for processor speeds above 2GHz */
49 half_freqSystemBus
= sysInfo
->freqSystemBus
/2;
50 sysInfo
->freqProcessor
= e500_ratio
*half_freqSystemBus
;
52 /* Note: freqDDRBus is the MCLK frequency, not the data rate. */
53 sysInfo
->freqDDRBus
= sysInfo
->freqSystemBus
;
55 #ifdef CONFIG_DDR_CLK_FREQ
57 u32 ddr_ratio
= ((gur
->porpllsr
) & MPC85xx_PORPLLSR_DDR_RATIO
)
58 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT
;
60 sysInfo
->freqDDRBus
= ddr_ratio
* CONFIG_DDR_CLK_FREQ
;
70 volatile ccsr_gur_t
*gur
= (void *) CFG_MPC85xx_GUTS_ADDR
;
72 #if defined(CONFIG_CPM2)
73 volatile ccsr_cpm_t
*cpm
= (ccsr_cpm_t
*)CFG_MPC85xx_CPM_ADDR
;
76 /* set VCO = 4 * BRG */
77 cpm
->im_cpm_intctl
.sccr
&= 0xfffffffc;
78 sccr
= cpm
->im_cpm_intctl
.sccr
;
79 dfbrg
= (sccr
& SCCR_DFBRG_MSK
) >> SCCR_DFBRG_SHIFT
;
81 get_sys_info (&sys_info
);
82 gd
->cpu_clk
= sys_info
.freqProcessor
;
83 gd
->bus_clk
= sys_info
.freqSystemBus
;
84 gd
->mem_clk
= sys_info
.freqDDRBus
;
87 * The base clock for I2C depends on the actual SOC. Unfortunately,
88 * there is no pattern that can be used to determine the frequency, so
89 * the only choice is to look up the actual SOC number and use the value
90 * for that SOC. This information is taken from application note
93 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
94 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
95 gd
->i2c1_clk
= sys_info
.freqSystemBus
;
96 #elif defined(CONFIG_MPC8544)
98 * On the 8544, the I2C clock is the same as the SEC clock. This can be
99 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
100 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
101 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
102 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
104 if (gur
->pordevsr2
& MPC85xx_PORDEVSR2_SEC_CFG
)
105 gd
->i2c1_clk
= sys_info
.freqSystemBus
/ 2;
107 gd
->i2c1_clk
= sys_info
.freqSystemBus
/ 3;
109 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
110 gd
->i2c1_clk
= sys_info
.freqSystemBus
/ 2;
112 gd
->i2c2_clk
= gd
->i2c1_clk
;
114 #if defined(CONFIG_MPC8536)
115 gd
->sdhc_clk
= gd
->bus_clk
/ 2;
118 #if defined(CONFIG_CPM2)
119 gd
->vco_out
= 2*sys_info
.freqSystemBus
;
120 gd
->cpm_clk
= gd
->vco_out
/ 2;
121 gd
->scc_clk
= gd
->vco_out
/ 4;
122 gd
->brg_clk
= gd
->vco_out
/ (1 << (2 * (dfbrg
+ 1)));
125 if(gd
->cpu_clk
!= 0) return (0);
130 /********************************************
132 * return system bus freq in Hz
133 *********************************************/
134 ulong
get_bus_freq (ulong dummy
)
139 /********************************************
141 * return ddr bus freq in Hz
142 *********************************************/
143 ulong
get_ddr_freq (ulong dummy
)