cpu/mpc86xx/cpu.c

   1 /*
   2  * Copyright 2006 Freescale Semiconductor
   3  * Jeff Brown
   4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <watchdog.h>
  27 #include <command.h>
  28 #include <asm/cache.h>
  29 #include <mpc86xx.h>
  30
  31 #if defined(CONFIG_OF_FLAT_TREE)
  32 #include <ft_build.h>
  33 #endif
  34
  35 int
  36 checkcpu(void)
  37 {
  38         sys_info_t sysinfo;
  39         uint pvr, svr;
  40         uint ver;
  41         uint major, minor;
  42         uint lcrr;              /* local bus clock ratio register */
  43         uint clkdiv;            /* clock divider portion of lcrr */
  44
  45         puts("Freescale PowerPC\n");
  46
  47         pvr = get_pvr();
  48         ver = PVR_VER(pvr);
  49         major = PVR_MAJ(pvr);
  50         minor = PVR_MIN(pvr);
  51
  52         puts("CPU:\n");
  53         puts("    Core: ");
  54
  55         switch (ver) {
  56         case PVR_VER(PVR_86xx):
  57                 puts("E600");
  58                 break;
  59         default:
  60                 puts("Unknown");
  61                 break;
  62         }
  63         printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
  64
  65         svr = get_svr();
  66         ver = SVR_VER(svr);
  67         major = SVR_MAJ(svr);
  68         minor = SVR_MIN(svr);
  69
  70         puts("    System: ");
  71         switch (ver) {
  72         case SVR_8641:
  73             if (SVR_SUBVER(svr) == 1) {
  74                 puts("8641D");
  75             } else {
  76                 puts("8641");
  77             }
  78             break;
  79         default:
  80                 puts("Unknown");
  81                 break;
  82         }
  83         printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  84
  85         get_sys_info(&sysinfo);
  86
  87         puts("    Clocks: ");
  88         printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
  89         printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
  90         printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
  91
  92 #if defined(CFG_LBC_LCRR)
  93         lcrr = CFG_LBC_LCRR;
  94 #else
  95         {
  96                 volatile immap_t *immap = (immap_t *) CFG_IMMR;
  97                 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
  98
  99                 lcrr = lbc->lcrr;
 100         }
 101 #endif
 102         clkdiv = lcrr & 0x0f;
 103         if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
 104                 printf("LBC:%4lu MHz\n",
 105                        sysinfo.freqSystemBus / 1000000 / clkdiv);
 106         } else {
 107                 printf("    LBC: unknown (lcrr: 0x%08x)\n", lcrr);
 108         }
 109
 110         puts("    L2: ");
 111         if (get_l2cr() & 0x80000000)
 112                 puts("Enabled\n");
 113         else
 114                 puts("Disabled\n");
 115
 116         return 0;
 117 }
 118
 119
 120 static inline void
 121 soft_restart(unsigned long addr)
 122 {
 123 #ifndef CONFIG_MPC8641HPCN
 124
 125         /*
 126          * SRR0 has system reset vector, SRR1 has default MSR value
 127          * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
 128          */
 129
 130         __asm__ __volatile__ ("mtspr    26, %0"         :: "r" (addr));
 131         __asm__ __volatile__ ("li       4, (1 << 6)"    ::: "r4");
 132         __asm__ __volatile__ ("mtspr    27, 4");
 133         __asm__ __volatile__ ("rfi");
 134
 135 #else /* CONFIG_MPC8641HPCN */
 136
 137         out8(PIXIS_BASE + PIXIS_RST, 0);
 138
 139 #endif /* !CONFIG_MPC8641HPCN */
 140
 141         while (1) ;             /* not reached */
 142 }
 143
 144
 145 /*
 146  * No generic way to do board reset. Simply call soft_reset.
 147  */
 148 void
 149 do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 150 {
 151 #ifndef CONFIG_MPC8641HPCN
 152
 153 #ifdef CFG_RESET_ADDRESS
 154         ulong addr = CFG_RESET_ADDRESS;
 155 #else
 156         /*
 157          * note: when CFG_MONITOR_BASE points to a RAM address,
 158          * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
 159          * address. Better pick an address known to be invalid on your
 160          * system and assign it to CFG_RESET_ADDRESS.
 161          */
 162         ulong addr = CFG_MONITOR_BASE - sizeof(ulong);
 163 #endif
 164
 165         /* flush and disable I/D cache */
 166         __asm__ __volatile__ ("mfspr    3, 1008"        ::: "r3");
 167         __asm__ __volatile__ ("ori      5, 5, 0xcc00"   ::: "r5");
 168         __asm__ __volatile__ ("ori      4, 3, 0xc00"    ::: "r4");
 169         __asm__ __volatile__ ("andc     5, 3, 5"        ::: "r5");
 170         __asm__ __volatile__ ("sync");
 171         __asm__ __volatile__ ("mtspr    1008, 4");
 172         __asm__ __volatile__ ("isync");
 173         __asm__ __volatile__ ("sync");
 174         __asm__ __volatile__ ("mtspr    1008, 5");
 175         __asm__ __volatile__ ("isync");
 176         __asm__ __volatile__ ("sync");
 177
 178         soft_restart(addr);
 179
 180 #else /* CONFIG_MPC8641HPCN */
 181
 182         out8(PIXIS_BASE + PIXIS_RST, 0);
 183
 184 #endif /* !CONFIG_MPC8641HPCN */
 185
 186         while (1) ;             /* not reached */
 187 }
 188
 189
 190 /*
 191  * Get timebase clock frequency
 192  */
 193 unsigned long
 194 get_tbclk(void)
 195 {
 196         sys_info_t sys_info;
 197
 198         get_sys_info(&sys_info);
 199         return (sys_info.freqSystemBus + 3L) / 4L;
 200 }
 201
 202
 203 #if defined(CONFIG_WATCHDOG)
 204 void
 205 watchdog_reset(void)
 206 {
 207 }
 208 #endif  /* CONFIG_WATCHDOG */
 209
 210
 211 #if defined(CONFIG_DDR_ECC)
 212 void
 213 dma_init(void)
 214 {
 215         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 216         volatile ccsr_dma_t *dma = &immap->im_dma;
 217
 218         dma->satr0 = 0x00040000;
 219         dma->datr0 = 0x00040000;
 220         asm("sync; isync");
 221 }
 222
 223 uint
 224 dma_check(void)
 225 {
 226         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 227         volatile ccsr_dma_t *dma = &immap->im_dma;
 228         volatile uint status = dma->sr0;
 229
 230         /* While the channel is busy, spin */
 231         while ((status & 4) == 4) {
 232                 status = dma->sr0;
 233         }
 234
 235         if (status != 0) {
 236                 printf("DMA Error: status = %x\n", status);
 237         }
 238         return status;
 239 }
 240
 241 int
 242 dma_xfer(void *dest, uint count, void *src)
 243 {
 244         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 245         volatile ccsr_dma_t *dma = &immap->im_dma;
 246
 247         dma->dar0 = (uint) dest;
 248         dma->sar0 = (uint) src;
 249         dma->bcr0 = count;
 250         dma->mr0 = 0xf000004;
 251         asm("sync;isync");
 252         dma->mr0 = 0xf000005;
 253         asm("sync;isync");
 254         return dma_check();
 255 }
 256
 257 #endif  /* CONFIG_DDR_ECC */
 258
 259
 260 #ifdef CONFIG_OF_FLAT_TREE
 261 void
 262 ft_cpu_setup(void *blob, bd_t *bd)
 263 {
 264         u32 *p;
 265         ulong clock;
 266         int len;
 267
 268         clock = bd->bi_busfreq;
 269         p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
 270         if (p != NULL)
 271                 *p = cpu_to_be32(clock);
 272
 273         p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
 274         if (p != NULL)
 275                 *p = cpu_to_be32(clock);
 276
 277         p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
 278         if (p != NULL)
 279                 *p = cpu_to_be32(clock);
 280
 281 #if defined(CONFIG_TSEC1)
 282         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
 283         if (p != NULL)
 284                 memcpy(p, bd->bi_enetaddr, 6);
 285         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
 286         if (p)
 287                 memcpy(p, bd->bi_enetaddr, 6);
 288 #endif
 289
 290 #if defined(CONFIG_TSEC2)
 291         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
 292         if (p != NULL)
 293                 memcpy(p, bd->bi_enet1addr, 6);
 294         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
 295         if (p != NULL)
 296                 memcpy(p, bd->bi_enet1addr, 6);
 297 #endif
 298
 299 #if defined(CONFIG_TSEC3)
 300         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
 301         if (p != NULL)
 302                 memcpy(p, bd->bi_enet2addr, 6);
 303         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len);
 304         if (p != NULL)
 305                 memcpy(p, bd->bi_enet2addr, 6);
 306 #endif
 307
 308 #if defined(CONFIG_TSEC4)
 309         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
 310         if (p != NULL)
 311                 memcpy(p, bd->bi_enet3addr, 6);
 312         p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len);
 313         if (p != NULL)
 314                 memcpy(p, bd->bi_enet3addr, 6);
 315 #endif
 316
 317 }
 318 #endif