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git.ipfire.org Git - people/ms/u-boot.git/blob - cpu/mpc8xx/serial.c
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
31 #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
34 #define PROFF_SMC PROFF_SMC1
35 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
37 #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
40 #define PROFF_SMC PROFF_SMC2
41 #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
43 #elif defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
46 #define PROFF_SCC PROFF_SCC1
47 #define CPM_CR_CH_SCC CPM_CR_CH_SCC1
49 #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
52 #define PROFF_SCC PROFF_SCC2
53 #define CPM_CR_CH_SCC CPM_CR_CH_SCC2
55 #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
58 #define PROFF_SCC PROFF_SCC3
59 #define CPM_CR_CH_SCC CPM_CR_CH_SCC3
61 #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
64 #define PROFF_SCC PROFF_SCC4
65 #define CPM_CR_CH_SCC CPM_CR_CH_SCC4
67 #else /* CONFIG_8xx_CONS_? */
68 #error "console not correctly defined"
71 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
74 * Minimal serial functions needed to use one of the SMC ports
75 * as serial console interface.
78 int serial_init (void)
80 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
82 volatile smc_uart_t
*up
;
83 volatile cbd_t
*tbdf
, *rbdf
;
84 volatile cpm8xx_t
*cp
= &(im
->im_cpm
);
85 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
86 volatile iop8xx_t
*ip
= (iop8xx_t
*)&(im
->im_ioport
);
90 /* initialize pointers to SMC */
92 sp
= (smc_t
*) &(cp
->cp_smc
[SMC_INDEX
]);
93 up
= (smc_uart_t
*) &cp
->cp_dparam
[PROFF_SMC
];
95 /* Disable transmitter/receiver.
97 sp
->smc_smcmr
&= ~(SMCMR_REN
| SMCMR_TEN
);
101 im
->im_siu_conf
.sc_sdcr
= 1;
103 /* clear error conditions */
105 im
->im_sdma
.sdma_sdsr
= CFG_SDSR
;
107 im
->im_sdma
.sdma_sdsr
= 0x83;
110 /* clear SDMA interrupt mask */
112 im
->im_sdma
.sdma_sdmr
= CFG_SDMR
;
114 im
->im_sdma
.sdma_sdmr
= 0x00;
117 #if defined(CONFIG_8xx_CONS_SMC1)
118 /* Use Port B for SMC1 instead of other functions.
120 cp
->cp_pbpar
|= 0x000000c0;
121 cp
->cp_pbdir
&= ~0x000000c0;
122 cp
->cp_pbodr
&= ~0x000000c0;
123 #else /* CONFIG_8xx_CONS_SMC2 */
124 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
125 /* Use Port A for SMC2 instead of other functions.
127 ip
->iop_papar
|= 0x00c0;
128 ip
->iop_padir
&= ~0x00c0;
129 ip
->iop_paodr
&= ~0x00c0;
130 # else /* must be a 860 then */
131 /* Use Port B for SMC2 instead of other functions.
133 cp
->cp_pbpar
|= 0x00000c00;
134 cp
->cp_pbdir
&= ~0x00000c00;
135 cp
->cp_pbodr
&= ~0x00000c00;
139 #if defined(CONFIG_FADS)
141 #if defined(CONFIG_8xx_CONS_SMC1)
142 *((uint
*) BCSR1
) &= ~BCSR1_RS232EN_1
;
144 *((uint
*) BCSR1
) &= ~BCSR1_RS232EN_2
;
146 #endif /* CONFIG_FADS */
148 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
149 /* Enable Monitor Port Transceiver */
150 *((uchar
*) BCSR0
) |= BCSR0_ENMONXCVR
;
151 #endif /* CONFIG_RPXLITE */
153 /* Set the physical address of the host memory buffers in
154 * the buffer descriptors.
157 #ifdef CFG_ALLOC_DPRAM
158 dpaddr
= dpram_alloc_align (sizeof(cbd_t
)*2 + 2, 8) ;
160 dpaddr
= CPM_SERIAL_BASE
;
163 /* Allocate space for two buffer descriptors in the DP ram.
164 * For now, this address seems OK, but it may have to
165 * change with newer versions of the firmware.
166 * damm: allocating space after the two buffers for rx/tx data
169 rbdf
= (cbd_t
*)&cp
->cp_dpmem
[dpaddr
];
170 rbdf
->cbd_bufaddr
= (uint
) (rbdf
+2);
173 tbdf
->cbd_bufaddr
= ((uint
) (rbdf
+2)) + 1;
176 /* Set up the uart parameters in the parameter ram.
178 up
->smc_rbase
= dpaddr
;
179 up
->smc_tbase
= dpaddr
+sizeof(cbd_t
);
180 up
->smc_rfcr
= SMC_EB
;
181 up
->smc_tfcr
= SMC_EB
;
183 #if defined(CONFIG_MBX)
185 #endif /* CONFIG_MBX */
187 /* Set UART mode, 8 bit, no parity, one stop.
188 * Enable receive and transmit.
190 sp
->smc_smcmr
= smcr_mk_clen(9) | SMCMR_SM_UART
;
192 /* Mask all interrupts and remove anything pending.
197 /* Set up the baud rate generator.
201 /* Make the first buffer the only buffer.
203 tbdf
->cbd_sc
|= BD_SC_WRAP
;
204 rbdf
->cbd_sc
|= BD_SC_EMPTY
| BD_SC_WRAP
;
206 /* Single character receive.
211 /* Initialize Tx/Rx parameters.
214 while (cp
->cp_cpcr
& CPM_CR_FLG
) /* wait if cp is busy */
217 cp
->cp_cpcr
= mk_cr_cmd(CPM_CR_CH_SMC
, CPM_CR_INIT_TRX
) | CPM_CR_FLG
;
219 while (cp
->cp_cpcr
& CPM_CR_FLG
) /* wait if cp is busy */
222 /* Enable transmitter/receiver.
224 sp
->smc_smcmr
|= SMCMR_REN
| SMCMR_TEN
;
232 DECLARE_GLOBAL_DATA_PTR
;
234 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
235 volatile cpm8xx_t
*cp
= &(im
->im_cpm
);
237 /* Set up the baud rate generator.
238 * See 8xx_io/commproc.c for details.
243 cp
->cp_simode
= 0x00000000;
246 (((gd
->cpu_clk
/ 16 / gd
->baudrate
)-1) << 1) | CPM_BRG_EN
;
249 #ifdef CONFIG_MODEM_SUPPORT
250 void disable_putc(void)
252 DECLARE_GLOBAL_DATA_PTR
;
256 void enable_putc(void)
258 DECLARE_GLOBAL_DATA_PTR
;
264 serial_putc(const char c
)
266 volatile cbd_t
*tbdf
;
268 volatile smc_uart_t
*up
;
269 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
270 volatile cpm8xx_t
*cpmp
= &(im
->im_cpm
);
272 #ifdef CONFIG_MODEM_SUPPORT
273 DECLARE_GLOBAL_DATA_PTR
;
282 up
= (smc_uart_t
*)&cpmp
->cp_dparam
[PROFF_SMC
];
284 tbdf
= (cbd_t
*)&cpmp
->cp_dpmem
[up
->smc_tbase
];
286 /* Wait for last character to go.
289 buf
= (char *)tbdf
->cbd_bufaddr
;
292 tbdf
->cbd_datlen
= 1;
293 tbdf
->cbd_sc
|= BD_SC_READY
;
296 while (tbdf
->cbd_sc
& BD_SC_READY
) {
305 volatile cbd_t
*rbdf
;
306 volatile unsigned char *buf
;
307 volatile smc_uart_t
*up
;
308 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
309 volatile cpm8xx_t
*cpmp
= &(im
->im_cpm
);
312 up
= (smc_uart_t
*)&cpmp
->cp_dparam
[PROFF_SMC
];
314 rbdf
= (cbd_t
*)&cpmp
->cp_dpmem
[up
->smc_rbase
];
316 /* Wait for character to show up.
318 buf
= (unsigned char *)rbdf
->cbd_bufaddr
;
320 while (rbdf
->cbd_sc
& BD_SC_EMPTY
)
324 rbdf
->cbd_sc
|= BD_SC_EMPTY
;
332 volatile cbd_t
*rbdf
;
333 volatile smc_uart_t
*up
;
334 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
335 volatile cpm8xx_t
*cpmp
= &(im
->im_cpm
);
337 up
= (smc_uart_t
*)&cpmp
->cp_dparam
[PROFF_SMC
];
339 rbdf
= (cbd_t
*)&cpmp
->cp_dpmem
[up
->smc_rbase
];
341 return(!(rbdf
->cbd_sc
& BD_SC_EMPTY
));
344 #else /* ! CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */
346 int serial_init (void)
348 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
350 volatile scc_uart_t
*up
;
351 volatile cbd_t
*tbdf
, *rbdf
;
352 volatile cpm8xx_t
*cp
= &(im
->im_cpm
);
354 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
355 volatile iop8xx_t
*ip
= (iop8xx_t
*)&(im
->im_ioport
);
358 /* initialize pointers to SCC */
360 sp
= (scc_t
*) &(cp
->cp_scc
[SCC_INDEX
]);
361 up
= (scc_uart_t
*) &cp
->cp_dparam
[PROFF_SCC
];
363 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
364 { /* Disable Ethernet, enable Serial */
368 c
&= ~0x40; /* enable COM3 */
369 c
|= 0x80; /* disable Ethernet */
373 cp
->cp_pbpar
|= 0x2000;
374 cp
->cp_pbdat
|= 0x2000;
375 cp
->cp_pbdir
|= 0x2000;
377 #endif /* CONFIG_LWMON */
379 /* Disable transmitter/receiver.
381 sp
->scc_gsmrl
&= ~(SCC_GSMRL_ENR
| SCC_GSMRL_ENT
);
383 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
385 * The MPC850 has SCC3 on Port B
387 cp
->cp_pbpar
|= 0x06;
388 cp
->cp_pbdir
&= ~0x06;
389 cp
->cp_pbodr
&= ~0x06;
391 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
393 * Standard configuration for SCC's is on Part A
395 ip
->iop_papar
|= ((3 << (2 * SCC_INDEX
)));
396 ip
->iop_padir
&= ~((3 << (2 * SCC_INDEX
)));
397 ip
->iop_paodr
&= ~((3 << (2 * SCC_INDEX
)));
400 * The IP860 has SCC3 and SCC4 on Port D
402 ip
->iop_pdpar
|= ((3 << (2 * SCC_INDEX
)));
405 /* Allocate space for two buffer descriptors in the DP ram.
408 #ifdef CFG_ALLOC_DPRAM
409 dpaddr
= dpram_alloc_align (sizeof(cbd_t
)*2 + 2, 8) ;
411 dpaddr
= CPM_SERIAL_BASE
;
416 im
->im_siu_conf
.sc_sdcr
= 0x0001;
418 /* Set the physical address of the host memory buffers in
419 * the buffer descriptors.
422 rbdf
= (cbd_t
*)&cp
->cp_dpmem
[dpaddr
];
423 rbdf
->cbd_bufaddr
= (uint
) (rbdf
+2);
426 tbdf
->cbd_bufaddr
= ((uint
) (rbdf
+2)) + 1;
429 /* Set up the baud rate generator.
433 /* Set up the uart parameters in the parameter ram.
435 up
->scc_genscc
.scc_rbase
= dpaddr
;
436 up
->scc_genscc
.scc_tbase
= dpaddr
+sizeof(cbd_t
);
438 /* Initialize Tx/Rx parameters.
440 while (cp
->cp_cpcr
& CPM_CR_FLG
) /* wait if cp is busy */
442 cp
->cp_cpcr
= mk_cr_cmd(CPM_CR_CH_SCC
, CPM_CR_INIT_TRX
) | CPM_CR_FLG
;
444 while (cp
->cp_cpcr
& CPM_CR_FLG
) /* wait if cp is busy */
447 up
->scc_genscc
.scc_rfcr
= SCC_EB
| 0x05;
448 up
->scc_genscc
.scc_tfcr
= SCC_EB
| 0x05;
450 up
->scc_genscc
.scc_mrblr
= 1; /* Single character receive */
451 up
->scc_maxidl
= 0; /* disable max idle */
452 up
->scc_brkcr
= 1; /* send one break character on stop TX */
460 up
->scc_char1
= 0x8000;
461 up
->scc_char2
= 0x8000;
462 up
->scc_char3
= 0x8000;
463 up
->scc_char4
= 0x8000;
464 up
->scc_char5
= 0x8000;
465 up
->scc_char6
= 0x8000;
466 up
->scc_char7
= 0x8000;
467 up
->scc_char8
= 0x8000;
468 up
->scc_rccm
= 0xc0ff;
470 /* Set low latency / small fifo.
472 sp
->scc_gsmrh
= SCC_GSMRH_RFW
;
474 /* Set SCC(x) clock mode to 16x
475 * See 8xx_io/commproc.c for details.
480 /* Set UART mode, clock divider 16 on Tx and Rx
483 (SCC_GSMRL_MODE_UART
| SCC_GSMRL_TDCR_16
| SCC_GSMRL_RDCR_16
);
485 sp
->scc_psmr
|= SCU_PSMR_CL
;
487 /* Mask all interrupts and remove anything pending.
490 sp
->scc_scce
= 0xffff;
491 sp
->scc_dsr
= 0x7e7e;
492 sp
->scc_psmr
= 0x3000;
494 /* Make the first buffer the only buffer.
496 tbdf
->cbd_sc
|= BD_SC_WRAP
;
497 rbdf
->cbd_sc
|= BD_SC_EMPTY
| BD_SC_WRAP
;
499 /* Enable transmitter/receiver.
501 sp
->scc_gsmrl
|= (SCC_GSMRL_ENR
| SCC_GSMRL_ENT
);
509 DECLARE_GLOBAL_DATA_PTR
;
511 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
512 volatile cpm8xx_t
*cp
= &(im
->im_cpm
);
514 /* Set up the baud rate generator.
515 * See 8xx_io/commproc.c for details.
520 cp
->cp_sicr
&= ~(0x000000FF << (8 * SCC_INDEX
));
521 /* no |= needed, since BRG1 is 000 */
524 (((gd
->cpu_clk
/ 16 / gd
->baudrate
)-1) << 1) | CPM_BRG_EN
;
528 serial_putc(const char c
)
530 volatile cbd_t
*tbdf
;
532 volatile scc_uart_t
*up
;
533 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
534 volatile cpm8xx_t
*cpmp
= &(im
->im_cpm
);
539 up
= (scc_uart_t
*)&cpmp
->cp_dparam
[PROFF_SCC
];
541 tbdf
= (cbd_t
*)&cpmp
->cp_dpmem
[up
->scc_genscc
.scc_tbase
];
543 /* Wait for last character to go.
546 buf
= (char *)tbdf
->cbd_bufaddr
;
549 tbdf
->cbd_datlen
= 1;
550 tbdf
->cbd_sc
|= BD_SC_READY
;
553 while (tbdf
->cbd_sc
& BD_SC_READY
) {
562 volatile cbd_t
*rbdf
;
563 volatile unsigned char *buf
;
564 volatile scc_uart_t
*up
;
565 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
566 volatile cpm8xx_t
*cpmp
= &(im
->im_cpm
);
569 up
= (scc_uart_t
*)&cpmp
->cp_dparam
[PROFF_SCC
];
571 rbdf
= (cbd_t
*)&cpmp
->cp_dpmem
[up
->scc_genscc
.scc_rbase
];
573 /* Wait for character to show up.
575 buf
= (unsigned char *)rbdf
->cbd_bufaddr
;
577 while (rbdf
->cbd_sc
& BD_SC_EMPTY
)
581 rbdf
->cbd_sc
|= BD_SC_EMPTY
;
589 volatile cbd_t
*rbdf
;
590 volatile scc_uart_t
*up
;
591 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
592 volatile cpm8xx_t
*cpmp
= &(im
->im_cpm
);
594 up
= (scc_uart_t
*)&cpmp
->cp_dparam
[PROFF_SCC
];
596 rbdf
= (cbd_t
*)&cpmp
->cp_dpmem
[up
->scc_genscc
.scc_rbase
];
598 return(!(rbdf
->cbd_sc
& BD_SC_EMPTY
));
601 #endif /* CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */
605 serial_puts (const char *s
)
613 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
616 kgdb_serial_init(void)
618 #if defined(CONFIG_8xx_CONS_SMC1)
619 serial_printf("[on SMC1] ");
620 #elif defined(CONFIG_8xx_CONS_SMC2)
621 serial_printf("[on SMC2] ");
622 #elif defined(CONFIG_8xx_CONS_SCC1)
623 serial_printf("[on SCC1] ");
624 #elif defined(CONFIG_8xx_CONS_SCC2)
625 serial_printf("[on SCC2] ");
626 #elif defined(CONFIG_8xx_CONS_SCC3)
627 serial_printf("[on SCC3] ");
628 #elif defined(CONFIG_8xx_CONS_SCC4)
629 serial_printf("[on SCC4] ");
640 putDebugStr (const char *str
)
648 return serial_getc();
652 kgdb_interruptible (int yes
)
656 #endif /* CFG_CMD_KGDB */
658 #endif /* CONFIG_8xx_CONS_NONE */