cpu/mpc8xx/serial.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <commproc.h>
  26 #include <command.h>
  27 #include <serial.h>
  28 #include <watchdog.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #if !defined(CONFIG_8xx_CONS_NONE)      /* No Console at all */
  33
  34 #if defined(CONFIG_8xx_CONS_SMC1)       /* Console on SMC1 */
  35 #define SMC_INDEX       0
  36 #define PROFF_SMC       PROFF_SMC1
  37 #define CPM_CR_CH_SMC   CPM_CR_CH_SMC1
  38
  39 #elif defined(CONFIG_8xx_CONS_SMC2)     /* Console on SMC2 */
  40 #define SMC_INDEX       1
  41 #define PROFF_SMC       PROFF_SMC2
  42 #define CPM_CR_CH_SMC   CPM_CR_CH_SMC2
  43
  44 #endif /* CONFIG_8xx_CONS_SMCx */
  45
  46 #if defined(CONFIG_8xx_CONS_SCC1)       /* Console on SCC1 */
  47 #define SCC_INDEX       0
  48 #define PROFF_SCC       PROFF_SCC1
  49 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC1
  50
  51 #elif defined(CONFIG_8xx_CONS_SCC2)     /* Console on SCC2 */
  52 #define SCC_INDEX       1
  53 #define PROFF_SCC       PROFF_SCC2
  54 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC2
  55
  56 #elif defined(CONFIG_8xx_CONS_SCC3)     /* Console on SCC3 */
  57 #define SCC_INDEX       2
  58 #define PROFF_SCC       PROFF_SCC3
  59 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC3
  60
  61 #elif defined(CONFIG_8xx_CONS_SCC4)     /* Console on SCC4 */
  62 #define SCC_INDEX       3
  63 #define PROFF_SCC       PROFF_SCC4
  64 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC4
  65
  66 #endif /* CONFIG_8xx_CONS_SCCx */
  67
  68 static void serial_setdivisor(volatile cpm8xx_t *cp)
  69 {
  70         int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
  71
  72         if(divisor/16>0x1000) {
  73                 /* bad divisor, assume 50Mhz clock and 9600 baud */
  74                 divisor=(50*1000*1000 + 8*9600)/16/9600;
  75         }
  76
  77 #ifdef CFG_BRGCLK_PRESCALE
  78         divisor /= CFG_BRGCLK_PRESCALE;
  79 #endif
  80
  81         if(divisor<=0x1000) {
  82                 cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
  83         } else {
  84                 cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
  85         }
  86 }
  87
  88 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
  89
  90 /*
  91  * Minimal serial functions needed to use one of the SMC ports
  92  * as serial console interface.
  93  */
  94
  95 static void smc_setbrg (void)
  96 {
  97         volatile immap_t *im = (immap_t *)CFG_IMMR;
  98         volatile cpm8xx_t *cp = &(im->im_cpm);
  99
 100         /* Set up the baud rate generator.
 101          * See 8xx_io/commproc.c for details.
 102          *
 103          * Wire BRG1 to SMCx
 104          */
 105
 106         cp->cp_simode = 0x00000000;
 107
 108         serial_setdivisor(cp);
 109 }
 110
 111 static int smc_init (void)
 112 {
 113         volatile immap_t *im = (immap_t *)CFG_IMMR;
 114         volatile smc_t *sp;
 115         volatile smc_uart_t *up;
 116         volatile cbd_t *tbdf, *rbdf;
 117         volatile cpm8xx_t *cp = &(im->im_cpm);
 118 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
 119         volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
 120 #endif
 121         uint    dpaddr;
 122
 123         /* initialize pointers to SMC */
 124
 125         sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
 126         up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
 127
 128         /* Disable transmitter/receiver.
 129         */
 130         sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 131
 132         /* Enable SDMA.
 133         */
 134         im->im_siu_conf.sc_sdcr = 1;
 135
 136         /* clear error conditions */
 137 #ifdef  CFG_SDSR
 138         im->im_sdma.sdma_sdsr = CFG_SDSR;
 139 #else
 140         im->im_sdma.sdma_sdsr = 0x83;
 141 #endif
 142
 143         /* clear SDMA interrupt mask */
 144 #ifdef  CFG_SDMR
 145         im->im_sdma.sdma_sdmr = CFG_SDMR;
 146 #else
 147         im->im_sdma.sdma_sdmr = 0x00;
 148 #endif
 149
 150 #if defined(CONFIG_8xx_CONS_SMC1)
 151         /* Use Port B for SMC1 instead of other functions.
 152         */
 153         cp->cp_pbpar |=  0x000000c0;
 154         cp->cp_pbdir &= ~0x000000c0;
 155         cp->cp_pbodr &= ~0x000000c0;
 156 #else   /* CONFIG_8xx_CONS_SMC2 */
 157 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
 158         /* Use Port A for SMC2 instead of other functions.
 159         */
 160         ip->iop_papar |=  0x00c0;
 161         ip->iop_padir &= ~0x00c0;
 162         ip->iop_paodr &= ~0x00c0;
 163 # else  /* must be a 860 then */
 164         /* Use Port B for SMC2 instead of other functions.
 165         */
 166         cp->cp_pbpar |=  0x00000c00;
 167         cp->cp_pbdir &= ~0x00000c00;
 168         cp->cp_pbodr &= ~0x00000c00;
 169 # endif
 170 #endif
 171
 172 #if defined(CONFIG_FADS) || defined(CONFIG_ADS)
 173         /* Enable RS232 */
 174 #if defined(CONFIG_8xx_CONS_SMC1)
 175         *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
 176 #else
 177         *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
 178 #endif
 179 #endif  /* CONFIG_FADS */
 180
 181 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
 182         /* Enable Monitor Port Transceiver */
 183         *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
 184 #endif /* CONFIG_RPXLITE */
 185
 186         /* Set the physical address of the host memory buffers in
 187          * the buffer descriptors.
 188          */
 189
 190 #ifdef CFG_ALLOC_DPRAM
 191         dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
 192 #else
 193         dpaddr = CPM_SERIAL_BASE ;
 194 #endif
 195
 196         /* Allocate space for two buffer descriptors in the DP ram.
 197          * For now, this address seems OK, but it may have to
 198          * change with newer versions of the firmware.
 199          * damm: allocating space after the two buffers for rx/tx data
 200          */
 201
 202         rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
 203         rbdf->cbd_bufaddr = (uint) (rbdf+2);
 204         rbdf->cbd_sc = 0;
 205         tbdf = rbdf + 1;
 206         tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
 207         tbdf->cbd_sc = 0;
 208
 209         /* Set up the uart parameters in the parameter ram.
 210         */
 211         up->smc_rbase = dpaddr;
 212         up->smc_tbase = dpaddr+sizeof(cbd_t);
 213         up->smc_rfcr = SMC_EB;
 214         up->smc_tfcr = SMC_EB;
 215
 216 #if defined(CONFIG_MBX)
 217         board_serial_init();
 218 #endif  /* CONFIG_MBX */
 219
 220         /* Set UART mode, 8 bit, no parity, one stop.
 221          * Enable receive and transmit.
 222          */
 223         sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;
 224
 225         /* Mask all interrupts and remove anything pending.
 226         */
 227         sp->smc_smcm = 0;
 228         sp->smc_smce = 0xff;
 229
 230 #ifdef CFG_SPC1920_SMC1_CLK4 /* clock source is PLD */
 231         *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0xff;
 232 #else
 233         /* Set up the baud rate generator */
 234         smc_setbrg ();
 235 #endif
 236
 237         /* Make the first buffer the only buffer.
 238         */
 239         tbdf->cbd_sc |= BD_SC_WRAP;
 240         rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 241
 242         /* Single character receive.
 243         */
 244         up->smc_mrblr = 1;
 245         up->smc_maxidl = 0;
 246
 247         /* Initialize Tx/Rx parameters.
 248         */
 249
 250         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 251           ;
 252
 253         cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 254
 255         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 256           ;
 257
 258         /* Enable transmitter/receiver.
 259         */
 260         sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
 261
 262         return (0);
 263 }
 264
 265 static void
 266 smc_putc(const char c)
 267 {
 268         volatile cbd_t          *tbdf;
 269         volatile char           *buf;
 270         volatile smc_uart_t     *up;
 271         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 272         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 273
 274 #ifdef CONFIG_MODEM_SUPPORT
 275         if (gd->be_quiet)
 276                 return;
 277 #endif
 278
 279         if (c == '\n')
 280                 smc_putc ('\r');
 281
 282         up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
 283
 284         tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
 285
 286         /* Wait for last character to go.
 287         */
 288
 289         buf = (char *)tbdf->cbd_bufaddr;
 290
 291         *buf = c;
 292         tbdf->cbd_datlen = 1;
 293         tbdf->cbd_sc |= BD_SC_READY;
 294         __asm__("eieio");
 295
 296         while (tbdf->cbd_sc & BD_SC_READY) {
 297                 WATCHDOG_RESET ();
 298                 __asm__("eieio");
 299         }
 300 }
 301
 302 static void
 303 smc_puts (const char *s)
 304 {
 305         while (*s) {
 306                 smc_putc (*s++);
 307         }
 308 }
 309
 310 static int
 311 smc_getc(void)
 312 {
 313         volatile cbd_t          *rbdf;
 314         volatile unsigned char  *buf;
 315         volatile smc_uart_t     *up;
 316         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 317         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 318         unsigned char           c;
 319
 320         up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
 321
 322         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
 323
 324         /* Wait for character to show up.
 325         */
 326         buf = (unsigned char *)rbdf->cbd_bufaddr;
 327
 328         while (rbdf->cbd_sc & BD_SC_EMPTY)
 329                 WATCHDOG_RESET ();
 330
 331         c = *buf;
 332         rbdf->cbd_sc |= BD_SC_EMPTY;
 333
 334         return(c);
 335 }
 336
 337 static int
 338 smc_tstc(void)
 339 {
 340         volatile cbd_t          *rbdf;
 341         volatile smc_uart_t     *up;
 342         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 343         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 344
 345         up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
 346
 347         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
 348
 349         return(!(rbdf->cbd_sc & BD_SC_EMPTY));
 350 }
 351
 352 struct serial_device serial_smc_device =
 353 {
 354         "serial_smc",
 355         "SMC",
 356         smc_init,
 357         smc_setbrg,
 358         smc_getc,
 359         smc_tstc,
 360         smc_putc,
 361         smc_puts,
 362 };
 363
 364 #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
 365
 366 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
 367     defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
 368
 369 static void
 370 scc_setbrg (void)
 371 {
 372         volatile immap_t *im = (immap_t *)CFG_IMMR;
 373         volatile cpm8xx_t *cp = &(im->im_cpm);
 374
 375         /* Set up the baud rate generator.
 376          * See 8xx_io/commproc.c for details.
 377          *
 378          * Wire BRG1 to SCCx
 379          */
 380
 381         cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
 382
 383         serial_setdivisor(cp);
 384 }
 385
 386 static int scc_init (void)
 387 {
 388         volatile immap_t *im = (immap_t *)CFG_IMMR;
 389         volatile scc_t *sp;
 390         volatile scc_uart_t *up;
 391         volatile cbd_t *tbdf, *rbdf;
 392         volatile cpm8xx_t *cp = &(im->im_cpm);
 393         uint     dpaddr;
 394 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
 395         volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
 396 #endif
 397
 398         /* initialize pointers to SCC */
 399
 400         sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
 401         up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
 402
 403 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
 404     {   /* Disable Ethernet, enable Serial */
 405         uchar c;
 406
 407         c = pic_read  (0x61);
 408         c &= ~0x40;     /* enable COM3 */
 409         c |=  0x80;     /* disable Ethernet */
 410         pic_write (0x61, c);
 411
 412         /* enable RTS2 */
 413         cp->cp_pbpar |=  0x2000;
 414         cp->cp_pbdat |=  0x2000;
 415         cp->cp_pbdir |=  0x2000;
 416     }
 417 #endif  /* CONFIG_LWMON */
 418
 419         /* Disable transmitter/receiver.
 420         */
 421         sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 422
 423 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
 424         /*
 425          * The MPC850 has SCC3 on Port B
 426          */
 427         cp->cp_pbpar |=  0x06;
 428         cp->cp_pbdir &= ~0x06;
 429         cp->cp_pbodr &= ~0x06;
 430
 431 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
 432         /*
 433          * Standard configuration for SCC's is on Part A
 434          */
 435         ip->iop_papar |=  ((3 << (2 * SCC_INDEX)));
 436         ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
 437         ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
 438 #else
 439         /*
 440          * The IP860 has SCC3 and SCC4 on Port D
 441          */
 442         ip->iop_pdpar |=  ((3 << (2 * SCC_INDEX)));
 443 #endif
 444
 445         /* Allocate space for two buffer descriptors in the DP ram.
 446          */
 447
 448 #ifdef CFG_ALLOC_DPRAM
 449         dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
 450 #else
 451         dpaddr = CPM_SERIAL2_BASE ;
 452 #endif
 453
 454         /* Enable SDMA.
 455         */
 456         im->im_siu_conf.sc_sdcr = 0x0001;
 457
 458         /* Set the physical address of the host memory buffers in
 459          * the buffer descriptors.
 460          */
 461
 462         rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
 463         rbdf->cbd_bufaddr = (uint) (rbdf+2);
 464         rbdf->cbd_sc = 0;
 465         tbdf = rbdf + 1;
 466         tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
 467         tbdf->cbd_sc = 0;
 468
 469         /* Set up the baud rate generator.
 470         */
 471         scc_setbrg ();
 472
 473         /* Set up the uart parameters in the parameter ram.
 474         */
 475         up->scc_genscc.scc_rbase = dpaddr;
 476         up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
 477
 478         /* Initialize Tx/Rx parameters.
 479         */
 480         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 481                 ;
 482         cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 483
 484         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 485                 ;
 486
 487         up->scc_genscc.scc_rfcr  = SCC_EB | 0x05;
 488         up->scc_genscc.scc_tfcr  = SCC_EB | 0x05;
 489
 490         up->scc_genscc.scc_mrblr = 1;   /* Single character receive */
 491         up->scc_maxidl = 0;             /* disable max idle */
 492         up->scc_brkcr  = 1;             /* send one break character on stop TX */
 493         up->scc_parec  = 0;
 494         up->scc_frmec  = 0;
 495         up->scc_nosec  = 0;
 496         up->scc_brkec  = 0;
 497         up->scc_uaddr1 = 0;
 498         up->scc_uaddr2 = 0;
 499         up->scc_toseq  = 0;
 500         up->scc_char1  = 0x8000;
 501         up->scc_char2  = 0x8000;
 502         up->scc_char3  = 0x8000;
 503         up->scc_char4  = 0x8000;
 504         up->scc_char5  = 0x8000;
 505         up->scc_char6  = 0x8000;
 506         up->scc_char7  = 0x8000;
 507         up->scc_char8  = 0x8000;
 508         up->scc_rccm   = 0xc0ff;
 509
 510         /* Set low latency / small fifo.
 511          */
 512         sp->scc_gsmrh = SCC_GSMRH_RFW;
 513
 514         /* Set SCC(x) clock mode to 16x
 515          * See 8xx_io/commproc.c for details.
 516          *
 517          * Wire BRG1 to SCCn
 518          */
 519
 520         /* Set UART mode, clock divider 16 on Tx and Rx
 521          */
 522         sp->scc_gsmrl &= ~0xF;
 523         sp->scc_gsmrl |=
 524                 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
 525
 526         sp->scc_psmr  = 0;
 527         sp->scc_psmr  |= SCU_PSMR_CL;
 528
 529         /* Mask all interrupts and remove anything pending.
 530         */
 531         sp->scc_sccm = 0;
 532         sp->scc_scce = 0xffff;
 533         sp->scc_dsr  = 0x7e7e;
 534         sp->scc_psmr = 0x3000;
 535
 536         /* Make the first buffer the only buffer.
 537         */
 538         tbdf->cbd_sc |= BD_SC_WRAP;
 539         rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 540
 541         /* Enable transmitter/receiver.
 542         */
 543         sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 544
 545         return (0);
 546 }
 547
 548 static void
 549 scc_putc(const char c)
 550 {
 551         volatile cbd_t          *tbdf;
 552         volatile char           *buf;
 553         volatile scc_uart_t     *up;
 554         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 555         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 556
 557 #ifdef CONFIG_MODEM_SUPPORT
 558         if (gd->be_quiet)
 559                 return;
 560 #endif
 561
 562         if (c == '\n')
 563                 scc_putc ('\r');
 564
 565         up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
 566
 567         tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
 568
 569         /* Wait for last character to go.
 570         */
 571
 572         buf = (char *)tbdf->cbd_bufaddr;
 573
 574         *buf = c;
 575         tbdf->cbd_datlen = 1;
 576         tbdf->cbd_sc |= BD_SC_READY;
 577         __asm__("eieio");
 578
 579         while (tbdf->cbd_sc & BD_SC_READY) {
 580                 __asm__("eieio");
 581                 WATCHDOG_RESET ();
 582         }
 583 }
 584
 585 static void
 586 scc_puts (const char *s)
 587 {
 588         while (*s) {
 589                 scc_putc (*s++);
 590         }
 591 }
 592
 593 static int
 594 scc_getc(void)
 595 {
 596         volatile cbd_t          *rbdf;
 597         volatile unsigned char  *buf;
 598         volatile scc_uart_t     *up;
 599         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 600         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 601         unsigned char           c;
 602
 603         up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
 604
 605         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
 606
 607         /* Wait for character to show up.
 608         */
 609         buf = (unsigned char *)rbdf->cbd_bufaddr;
 610
 611         while (rbdf->cbd_sc & BD_SC_EMPTY)
 612                 WATCHDOG_RESET ();
 613
 614         c = *buf;
 615         rbdf->cbd_sc |= BD_SC_EMPTY;
 616
 617         return(c);
 618 }
 619
 620 static int
 621 scc_tstc(void)
 622 {
 623         volatile cbd_t          *rbdf;
 624         volatile scc_uart_t     *up;
 625         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 626         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 627
 628         up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
 629
 630         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
 631
 632         return(!(rbdf->cbd_sc & BD_SC_EMPTY));
 633 }
 634
 635 struct serial_device serial_scc_device =
 636 {
 637         "serial_scc",
 638         "SCC",
 639         scc_init,
 640         scc_setbrg,
 641         scc_getc,
 642         scc_tstc,
 643         scc_putc,
 644         scc_puts,
 645 };
 646
 647 #endif  /* CONFIG_8xx_CONS_SCCx */
 648
 649 #ifdef CONFIG_MODEM_SUPPORT
 650 void disable_putc(void)
 651 {
 652         gd->be_quiet = 1;
 653 }
 654
 655 void enable_putc(void)
 656 {
 657         gd->be_quiet = 0;
 658 }
 659 #endif
 660
 661 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 662
 663 void
 664 kgdb_serial_init(void)
 665 {
 666         int i = -1;
 667
 668         if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
 669         {
 670 #if defined(CONFIG_8xx_CONS_SMC1)
 671                 i = 1;
 672 #elif defined(CONFIG_8xx_CONS_SMC2)
 673                 i = 2;
 674 #endif
 675         }
 676         else if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
 677         {
 678 #if defined(CONFIG_8xx_CONS_SCC1)
 679                 i = 1;
 680 #elif defined(CONFIG_8xx_CONS_SCC2)
 681                 i = 2;
 682 #elif defined(CONFIG_8xx_CONS_SCC3)
 683                 i = 3;
 684 #elif defined(CONFIG_8xx_CONS_SCC4)
 685                 i = 4;
 686 #endif
 687         }
 688
 689         if (i >= 0)
 690         {
 691                 serial_printf("[on %s%d] ", default_serial_console()->ctlr, i);
 692         }
 693 }
 694
 695 void
 696 putDebugChar (int c)
 697 {
 698         serial_putc (c);
 699 }
 700
 701 void
 702 putDebugStr (const char *str)
 703 {
 704         serial_puts (str);
 705 }
 706
 707 int
 708 getDebugChar (void)
 709 {
 710         return serial_getc();
 711 }
 712
 713 void
 714 kgdb_interruptible (int yes)
 715 {
 716         return;
 717 }
 718 #endif  /* CFG_CMD_KGDB */
 719
 720 #endif  /* CONFIG_8xx_CONS_NONE */